[dv] Improve riscv_csr_test
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- SystemVerilog
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Description
The current riscv_csr_test has a couple of issues and could have it's functionality expanded
- [ ] Deal correctly with read-only fields (it will generate instructions that write a value triggering an illegal instruction exception resulting in a test timeout)
- [ ] Implement an exception handler so illegal accesses, that weren't intended, generate a fail rather than a test timeout
- [ ] Intentionally test illegal CSR accesses
- [ ] Enable support of multiple Ibex configurations (https://github.com/lowRISC/ibex/issues/1333)
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating riscv_csr_test and reviewing how it handles read-only CSR fields and illegal accesses. Use the linked issue 1333 to understand the multiple Ibex configuration requirement. Done means the checklist items are implemented, including an exception handler that reports unintended illegal accesses as failures rather than timeouts.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100