[dv] Small architectural coverage issues to investigate

Nobody has claimed this yet.

Following analysis of the architectural coverage from RISC-DV there are a few small issues to investigate

- [ ] rv32i_misc_cg - Instructions in this group are getting executed but aren't appearing in coverage
- [ ] lw_cg - cp_lsu_hazard - Not seeing RAW memory hazard
- [ ] sw_cg - cp_lsu_hazard - Not seeing WAR memory hazard
- [ ] The illegal instruction space doesn't appear to be fully explored
- [ ] Some instructions (e.g. `lui`) haven't seen a RAW register hazard

The lack of RAW/WAR memory hazards isn't an issue as Ibex has no data cache or store/load buffers so there's no special handling these scenarios require.

The lack of register RAW hazards in a couple of instance isn't an issue as the RAW register hazard path is well explored and the gaps aren't special corner cases just oddities of RISC-V DV instruction generation (e.g. lack of RAW hazard for `lui`)

> estimate 8

Start by reviewing the RISC-DV architectural coverage results for rv32i_misc_cg, lw_cg, sw_cg, illegal instructions, and register hazards. Compare each reported gap with Ibex's supported behavior and RISC-V DV instruction generation; done means identifying which gaps are genuine coverage issues and which are expected limitations, with the findings documented or addressed.

Written by the indexing model from the issue text.