[dv] Add force pass and terminate functionality to UVM base test
Open
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
Some of the V2S tests need to force a test terminate on pass (as they need to corrupt various bits of Ibex state the test cannot continue once successful functioning of the security feature is seen). We should add a function to the base test class to deal with this cleanly
> Estimate 2
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the UVM base test class and the existing pass and termination handling used by the V2S tests. The issue does not name a file or test; done means the base test provides clean force-pass and terminate functionality that lets tests stop after successful security-feature validation.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 40/100