[rtl] Issues with memory and instruction fetch errors with branch prediction enabled
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- SystemVerilog
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Description
When `riscv_mem_error_test` is run with a config that includes a branch predictor failures are seen. These are around failures to take instruction faults and memory access faults.
It seems memory accesses next to branches can fail to produce the correct precise exception when a memory error response is seen.
For instruction faults it may be the branch prediction mechanism is failing to maintain correct error information leading to the execution of an instruction whose fetch saw an error response.
For now the branch prediction config will be removed from CI as that configuration is not a priority and these bugs will be addressed at a later date.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by running riscv_mem_error_test with the branch-predictor configuration and capture the instruction-fetch and memory-access fault failures. Trace the branch prediction and exception/error handling paths involved in those cases. Done means memory errors produce precise exceptions and an instruction whose fetch returned an error is not executed.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 42/100