Violation of the Data Independent Timing property for misaligned Load and Store Instructions

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## Observed Behavior
Ibex handles misaligned load and store Instructions by splitting them into two separate, aligned memory accesses.
This creates a data dependent execution time for these Instructions.
According to the specification, the **data_ind_timing** control bit should ensure that _execution times and power consumption of all instructions shall be independent of input data_.
However, this does not hold for load and store instructions and creates a possible timing side channel.

## Expected Behavior
I would expect Ibex to do either one of the following things:
1. Disable the "misaligned address feature" whenever the data_ind_timing bit is set to ensure all loads and stores require a single memory access. If a misaligned access is scheduled, Ibex should perform an aligned access and return bogus data. Further, the specification should tell the SW developer to ensure no misaligned access occurs.
2. In a different fix, Ibex could perform an additional dummy memory access (e.g. to an adjacent address), whenever an aligned load/store is issued while the data_ind_timing bit is set.

## Steps to reproduce the issue
Enable the data_ind_timing bit and set up a "secret" register value.
Issue a LW or LH with the secret register value as source and measure the time.
If value+offset result in an aligned access, the instruction will only trigger a single memory access.
If value+offset result in a misaligned access, the instruction will trigger two memory accesses.

In the trace, you can see an example with two processor instances.
The data independent timing bit gets set in both processors (via CSRRW) and the same LH instruction is executed.
However, r20 contains different values in the different instances (0 and 3) which causes a misaligned access only in instance 2.
As a consequence, instance 1 finishes earlier and is ready for the next instruction (id_in_ready_o) whereas instance 2 is requesting a second memory access (data_req_o).

## My Environment
I set up a set of formal SVA properties inside OneSpin to prove data independent execution of different instructions, both with and without the data_ind_timing bit.
For the proofs, I only consider the ibex_core, i.e., without cache or register file, in a 2-safety approach.
If you are interested in the details of the methodology, feel free to message me.

## My Results
I was able to prove that branches, division and (slow) multiplication have data dependent timing in the non-secure Ibex setting.
As described in the specification, when the data_ind_timing bit set, all of these issues get resolved.
However, I also got counterexamples for both load and store instructions, showing that the same instruction can cause different timing behavior based on register values.
This behavior does not change with an enabled data_ind_timing bit set.

**EDA tool and version:** OneSpin 360 DV - Version 2021.1.1

**Operating system:** Ubuntu Linux 18.04

**Version of the Ibex source code:** 90ff7ca6c3367da721dba13e91dfc98f782a5745

The issue names no source files or test entry points. Start by reproducing the aligned and misaligned LW/LH or store cases with data_ind_timing enabled, using the described two-processor comparison and formal SVA setup as references. Done requires an agreed design that removes the timing difference and corresponding specification and verification coverage.

Written by the indexing model from the issue text.