Teach auto-generated interrupt handlers to clear interrupts again
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- Dominant language
- SystemVerilog
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Description
It would be nice if we could customise our (new) sequences that drive interrupts to drop the interrupts again only when they were acknowledged. (Ibex has level-, rather than edge-triggered interrupts)
At the moment, the ISRs that come out of riscv-dv write to a magic "signature address". We could either use that for this purpose or could use something else. But the latter case would mean a modification of the (moribund?) riscv-dv project.
> estimate 4
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by tracing the new interrupt-driving sequences and the auto-generated ISRs from riscv-dv, especially their use of the magic signature address. Decide whether that address can carry the acknowledgement state or whether the riscv-dv integration needs changing; done means level-triggered interrupts are cleared only after acknowledgement.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100