mismatch between spike sim and rtl sim
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Description
Hi
I used the RTL code of ibex-pulpissimo-v6.1.1 and kicked off the following test case:
make TEST=riscv_arithmetic_basic_test ISS=spike ISA=rv32imc SEED=123
log:
out/seed-123/regr.log：
Could you give me any suggestions? how to debug it.
BTW, I replaced the "spike_log_to_trace_csv.py" by one in the master version of riscv-dv. Because the original one is fail to convert log into csv :
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Research direction
Start by reproducing the make TEST=riscv_arithmetic_basic_test ISS=spike ISA=rv32imc SEED=123 command and comparing the attached log with out/seed-123/regr.log. Inspect spike_log_to_trace_csv.py, including the reported master-version replacement, and consider the issue resolved when the log conversion works and the Spike and RTL simulation mismatch is explained.
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Assessment
- Tech stack
- python
- Domain
- testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100