Ibex does not reflect instruction memory changes to ICache
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- SystemVerilog
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Description
If ICache is enabled and a write to a cached instruction memory (which we are allowed to do) occurred, Ibex does not let ICache know such a store happened. As a result, cached instruction will not change inside ICache (but it will change in the memory component) and when PC will point to that address, Ibex will use the cached instruction. That causes mismatches between ISS and RTL.
It is probably not the most important corner case but I thought it might be good to document it as an issue for future.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No files, tests, or entry points are named. Start by tracing how stores reach cached instruction memory and how ICache is notified, then compare the behavior with the memory component. Done means instruction-cache contents reflect permitted instruction-memory writes and ISS and RTL no longer disagree.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100