Ask a question related to Ibex

Nobody has claimed this yet.

## My Environment

I wish to create a logic simulation environment while using ibex as a core. I have a question related on the structure of the core though.

1. Besides manual modification of the HDL, is there a way of including the Register File (FF) in the Instruction Decode stage ? In the current version I see that the RF is instantiated in the top module rather than in the ID whereas I would like to embed it in the core.
2. Is there a pre-written TB for the core in SystemVerilog ? I can't seem to find something relevant. Do i have to create a TB from scratch?
3. Is there a .tcl synthesis script that can be used instead of the yosys synthesis one?

**EDA tool and version:**

QuestaSIM 10.5c_4
Design Compiler Version S-2021.06-SP4 (for synthesis/DfT insertion)

**Operating system:**

OpenSUSE Leap 42.3 (EOL)

**Version of the Ibex source code:**

Latest

Start by reading the Ibex top module and instruction-decode structure referenced in the question, then inspect the existing core testbench and Yosys synthesis setup. Determine whether the repository documents a SystemVerilog testbench, register-file placement, or an alternative Tcl synthesis flow; done would require a clearly scoped documentation change or separate implementation issue.

Written by the indexing model from the issue text.