f4pga/f4pga-arch-defs

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FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Stars: 314
Forks: 121
Open beginner issues: 0
Indexed issues: 301

Dominant language: Jupyter Notebook
License: ISC
Last GitHub push: Aug 26, 2024
Latest indexed: Sep 15, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: help wanted good first issue
PR merge metrics: No merged PRs in 30d

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301 open issues indexed

Create a netlistsvg skin with routing muxes and logic muxes Open

arch-* in-progress type-docs type-sim

f4pga/f4pga-arch-defs#1 · 7 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Generate module block diagrams with symbolator Open

help wanted

f4pga/f4pga-arch-defs#7 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Generate pb_type.xml and model.xml from Verilog Open

in-progress lang-python lang-xml type-defs type-sim

f4pga/f4pga-arch-defs#8 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Write tests for the sim.v in some way. Open

help wanted type-sim

f4pga/f4pga-arch-defs#9 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a lot more tests for place and route Open

arch-* help wanted

f4pga/f4pga-arch-defs#15 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a "clock generator" tool Open

arch-* help wanted lang-python type-utils

f4pga/f4pga-arch-defs#16 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
All of these functions involve a fairly large number of calls to Yosys Open

todo :spiral_notepad:

f4pga/f4pga-arch-defs#41 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Change to using `specify` blocks for providing timing information. Open

arch-* lang-verilog type-sim

f4pga/f4pga-arch-defs#55 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Figure out how to write unit tests for the sim.v files. Open

help wanted type-sim

f4pga/f4pga-arch-defs#59 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a style guide for the sim.v files. Open

help wanted type-docs type-sim

f4pga/f4pga-arch-defs#60 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make all the Python files importable Open

help wanted lang-python

f4pga/f4pga-arch-defs#61 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Python scripts should only create output on success Open

help wanted lang-python type-utils

f4pga/f4pga-arch-defs#62 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make sure that the yosys generated output is deterministic Open

arch-* lang-python lang-verilog type-defs type-sim type-utils

f4pga/f4pga-arch-defs#63 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Make sure all dependencies are documented and available in the conda environment Open

arch-* dependencies type-build type-docs

f4pga/f4pga-arch-defs#69 · 6 comments · 1 reaction · 0 assignees · Indexed Sep 15, 2026
Refactor mux_gen util to be less one large file Open

help wanted lang-python type-utils

f4pga/f4pga-arch-defs#70 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add something to the empty.svg Open

type-defs type-sim type-utils

f4pga/f4pga-arch-defs#73 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Describe the DSP primitives in the Xilinx Series 7 Open

arch-xc7 in-progress lang-verilog lang-xml type-defs type-sim

f4pga/f4pga-arch-defs#81 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Port the iCE40 CLB to Verilog and generate the pb_type from it Open

arch-ice40 help wanted lang-verilog lang-xml todo :spiral_notepad: type-defs type-sim

f4pga/f4pga-arch-defs#92 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a Python library for generating VtR arch.xml file Open

arch-* enhancement lang-python lang-verilog lang-xml type-defs type-sim type-utils

f4pga/f4pga-arch-defs#99 · 7 comments · 0 reactions · 4 assignees · Indexed Sep 15, 2026
Pylint (or similar) on all python code as part of CI Open

arch-* lang-python type-build type-utils

f4pga/f4pga-arch-defs#102 · 6 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
rr_graph import: clean up pin import Open

arch-* in-progress lang-python type-utils

f4pga/f4pga-arch-defs#104 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Investigate cocotb import Open

arch-* dependencies type-sim

f4pga/f4pga-arch-defs#111 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Make cocotb Makefile use the make/types system Open

arch-* dependencies lang-makefile third-party type-build type-sim

f4pga/f4pga-arch-defs#112 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Get the LUT cascade on ice40 working Open

arch-ice40 lang-verilog lang-xml type-defs

f4pga/f4pga-arch-defs#139 · 2 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Get the carry chain on ice40 working Open

arch-ice40 lang-xml type-defs

f4pga/f4pga-arch-defs#140 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Describe the DSP primitives in the iCE40 UP5K Open

arch-ice40 lang-verilog lang-xml type-defs type-sim

f4pga/f4pga-arch-defs#142 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Create a LUT init permutation test Open

arch-base arch-ice40 arch-test lang-verilog lang-xml type-defs

f4pga/f4pga-arch-defs#143 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create an ice40 test for the packing of different types of flip flops together Open

arch-ice40 help wanted lang-verilog type-defs

f4pga/f4pga-arch-defs#144 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Write a test for the ice40 sb_carry block Open

arch-ice40 help wanted lang-cocotb lang-verilog lang-xml type-sim

f4pga/f4pga-arch-defs#146 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a "huge counter" stress test Open

arch-ice40 lang-verilog

f4pga/f4pga-arch-defs#153 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Import the arachne-pnr ice40 test suite Open

arch-ice40

f4pga/f4pga-arch-defs#154 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a "global reset" stress test for ice40 Open

arch-ice40 lang-verilog

f4pga/f4pga-arch-defs#155 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Get a proper model of the iCE40 IO tile into VPR Open

arch-ice40 enhancement in-progress lang-verilog lang-xml type-defs

f4pga/f4pga-arch-defs#158 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Generate the iCE40 routing graph rather than importing from icebox Open

arch-ice40 in-progress lang-python lang-xml type-vpr

f4pga/f4pga-arch-defs#159 · 4 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Import iCE40 timing information from icestorm Open

arch-ice40 enhancement in-progress lang-python lang-xml type-vpr

f4pga/f4pga-arch-defs#160 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Clean up the iCE40 global network when importing from icebox Open

arch-ice40 enhancement lang-python lang-xml type-vpr

f4pga/f4pga-arch-defs#161 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Generate netlistsvg images for each a sim model's modes Open

arch-* lang-verilog type-sim type-utils

f4pga/f4pga-arch-defs#167 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Figure out how to deal with "negative clock edges" in interconnect Open

arch-* arch-ice40 lang-python lang-verilog lang-xml type-defs type-sim

f4pga/f4pga-arch-defs#168 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
vlog_to_pbtype.xml tool outputting delay information for unconnected nets. Open

arch-* lang-python lang-verilog lang-xml type-defs type-sim type-utils

f4pga/f4pga-arch-defs#170 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Remove the 'virt' from the ice40 device name Open

arch-ice40 type-defs

f4pga/f4pga-arch-defs#177 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
ice40_import_routing_from_icebox: Remove duplicate info of ram pin offsets Open

arch-ice40 lang-python type-defs type-utils

f4pga/f4pga-arch-defs#179 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Write a Python library for decoding Xilinx Series 7 wire names Open

arch-xc7 good first issue help wanted lang-python type-utils

f4pga/f4pga-arch-defs#181 · 9 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Generate rr_graph file from routing data in Project Trellis Open

lang-python lang-xml type-utils type-vpr

f4pga/f4pga-arch-defs#193 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Improve the performance of the `ice40_import_routing_from_icebox.py` tool Open

arch-ice40 lang-python lang-xml type-utils

f4pga/f4pga-arch-defs#196 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
PCF flags: review behavior by parser Open

arch-ice40 lang-python lang-verilog type-benchmark type-build

f4pga/f4pga-arch-defs#202 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add timing constraints for all tests Open

arch-ice40 lang-verilog type-benchmark

f4pga/f4pga-arch-defs#203 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a "pretty printer" for the VTR .net file format Open

arch-* lang-python lang-xml type-vpr

f4pga/f4pga-arch-defs#209 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Remove .d output from utils/deps_xml.py once Makefile system is deprecated completely Open

f4pga/f4pga-arch-defs#218 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Convert all instances of comma seperate lists in CMake to semi-colon separated lists Open

f4pga/f4pga-arch-defs#219 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Find a CMake formatter that works Open

f4pga/f4pga-arch-defs#220 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

f4pga/f4pga-arch-defs

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