Generate pb_type.xml and model.xml from Verilog
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lang-python
lang-xml
type-defs
type-sim
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Description
Currently you need to manually create the `pb_type.xml` and `model.xml` files needed for vpr.
These should in theory be able to.be generated from the `sim.v` files using Yosys to generate a .json file and then a Python script to generate the XML from the json output.
Only thing to worry about is how parameters are handled here.
Might need some type of naming convention for the logic verse routing muxes too.
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