f4pga / f4pga/f4pga-arch-defs

Describe the DSP primitives in the Xilinx Series 7

Open
#81 1 comment 0 reactions 1 assignee Claimed by @elms View on GitHub
arch-xc7 in-progress lang-verilog lang-xml type-defs type-sim
Dominant language
Jupyter Notebook
Stars
314
Forks
121
No merged PRs in 30d

Description

It would be good to have good descriptions of the DSPs in the Series 7 architecture.

Contributor guide

No contributing guide indexed for this repository

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.