Change to using `specify` blocks for providing timing information.

Currently we are using Verilog attributes for timing information because Yosys doesn't support `specify` blocks. `specify` blocks are actually the proper way to provide timing information in Verilog, see below;

From http://verilog.renerta.com/source/vrg00044.htm;
> #### Example 1
> ```verilog
> module ...
> ...
> specify
> (In => Out) = (10);
> endspecify
> ...
> endmodule
> ```
> A specify block with only a path declaration. Delay between input In and output Out is 10 time units.
>
> #### Example 2
> ```verilog
> module ...
> ...
> specify
> specparam TRise = 10,
> TFall = 15;
> (In => Out) = (TRise, TFall) ;
> endspecify
> ...
> endmodule
> ```
> Specparam declaration with two parameters TRise and TFall to specify delays on rising transition and falling transition.
>
> #### Example 3
> ```verilog
> module ...
> ...
> specify
> specparam TRise = 10,
> TFall = 15;
> (In => Out) = (TRise, TFall) ;
> $setup(Data_in, posedge Clock, TRise) ;
> endspecify
> ...
> endmodule
> ```