Port the iCE40 CLB to Verilog and generate the pb_type from it

@daveshah1 [created a tool for generating Verilog to Routing XML files from verilog](https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/utils/vlog).

The goal is to eventually have fully simulatable Verilog descriptions of all the *actual* hardware (as opposed to the verilog macros for instantiating hardware). We have been working on this for the Artix 7 and we should do the same for the iCE40 hardware.