f4pga / f4pga/f4pga-arch-defs

Make sure that the yosys generated output is deterministic

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#63 1 comment 0 reactions 1 assignee Claimed by @daveshah1 View on GitHub
arch-* lang-python lang-verilog type-defs type-sim type-utils
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Description

It seems like the output from [`utils/vlog/`](utils/vlog) is not deterministic?

I think the order of the ports and delay_constant values seems to change? Are you sorting them? Any python dictionary needs to be sorted.

@daveshah1

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