lowRISC/ethernet
View on GitHubOpen-source memory-mapped Ethernet MAC for FPGA with RGMII interface
- Stars
- 23
- Forks
- 12
- Open beginner issues
- 0
- Indexed issues
- 10
- Dominant language
- SystemVerilog
- License
- No license data
- Last GitHub push
- Jul 27, 2026
- Latest indexed
- Sep 19, 2026
- Contributing guide
- No contributing guide
- Code of conduct
- No code of conduct
- Beginner labels
- No beginner labels indexed
- PR merge metrics
- No merged PRs in 30d
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Difficulty 5/5 Over a week Newbie friendliness 30/100
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Difficulty 4/5 3-5 days Newbie friendliness 35/100
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Difficulty 4/5 3-5 days Newbie friendliness 48/100
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Difficulty 4/5 3-5 days Newbie friendliness 48/100
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Difficulty 5/5 Over a week Newbie friendliness 35/100
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Difficulty 5/5 Over a week Newbie friendliness 35/100
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Difficulty 3/5 1-2 days Newbie friendliness 58/100
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Difficulty 4/5 3-5 days Newbie friendliness 48/100
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Difficulty 4/5 3-5 days Newbie friendliness 35/100
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Difficulty 5/5 Over a week Newbie friendliness 25/100