Dual port memories utilization
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- Dominant language
- SystemVerilog
- Stars
- 23
- Forks
- 12
- PR merge metrics
- No merged PRs in 30d
Description
Hi, I am working on the physical ASIC implementation of this IP. I am integrating this IP into a new chip and I am having issue with the xilinx dual ports dual clock memories instantiated into dualmem_widen8.sv and dualmem_widen.sv
I would like to know how this memories are used by the IP and if the two ports 2 clocks mem are strictly necessary for it.
Thank you
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
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Research direction
Start by reading dualmem_widen8.sv and dualmem_widen.sv, then trace where these memories are instantiated and how their ports and clocks connect to the Ethernet MAC. Done means documenting how the memories are used and whether both dual-port, dual-clock interfaces are required for the IP or can be replaced for ASIC integration.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, networking
- Issue type
- Documentation
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100