lowRISC / lowRISC/ethernet

TX/RX FSMs need refactoring

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Dominant language
SystemVerilog
Stars
23
Forks
12
PR merge metrics
No merged PRs in 30d

Description

These modules have a number of stylistic problems and poor documentation. Currently they do seem to work as intended but are something of a blackbox. Refactoring is worthwhile but low priority.

`axis_gmii_tx.sv`:
- The FSM transition logic is described by a `always @*` block that is over 200 lines and includes logic for driving outputs
- The some `logic` types are not reset
- Many flops sharing one processes
- Very little documentation for comments

`axis_gmii_rx.sv`:
- Inconsistent formatting, bad style, no comments
- Many `logic` types without reset
- Many flops sharing one process
- FSM transition logic and output logic described in the same `always @*` block
- Excessive reliance on processes over explicit combinational logic
- Not clear what the distinction is between `error_bad_frame`, `error_bad_fcs`, and `m_axis_tuser`

Contributor guide

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start with axis_gmii_tx.sv and axis_gmii_rx.sv, especially their FSM transition and output logic blocks. Compare the reset, process-sharing, formatting, and commenting concerns listed for each module, and clarify the distinction among error_bad_frame, error_bad_fcs, and m_axis_tuser. Done means both FSMs are easier to understand, consistently documented and styled, and their reset and logic organization issues are addressed.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot
Issue type
Refactor
Difficulty
4/5
Estimated time
3-5 days
Activity status
Quiet
Clarity
Mostly clear
Newbie friendliness
48/100

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