Assertions are disabled for Verilator
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- Dominant language
- SystemVerilog
- Stars
- 23
- Forks
- 12
- PR merge metrics
- No merged PRs in 30d
Description
`prim_assert.sv` (from Mocha/OpenTitan) defines the assertion macros, but it disables them for Verilator. Older versions of Verilator did not support assertions but the newest does so they should be enabled to improve checking in tests.
I have run the test suite in my local workspace with assertions 'manually' hacked to verify that they do not fail, but it would be best if we could do this in CI. This would require either:
- Modifying `prim_assert.sv` in the upstream
- Creating a flow for 'patching' dependencies (similar to the vendor.py flow used in Mocha/OT), but this is somewhat incompatible with using fusesoc.conf
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with prim_assert.sv and the existing test suite, then compare the vendor.py dependency-patching flow with fusesoc.conf. Choose and implement a maintainable way to enable assertions for Verilator, and verify in CI that the test suite passes with assertions enabled.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100