`ethernet_csr.sv` needs refactoring
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- Dominant language
- SystemVerilog
- Stars
- 23
- Forks
- 12
- PR merge metrics
- No merged PRs in 30d
Description
`ethernet_csr.sv` works but is a little bit difficult to read. It would be best to migrate to an automated register generator flow to avoid going out of sync with RDL
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading `ethernet_csr.sv` and identify how its registers relate to the RDL source. The issue does not name an automated generator, entry point, or tests, so determine the project’s intended register-generation flow before starting. Done means the CSR is generated through that flow and no longer risks going out of sync with the RDL.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, networking
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100