Test 'TX write during TX' _can_ fail
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- Dominant language
- SystemVerilog
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- 23
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Description
Writing to TX buffer while TX is ongoing is illegal and behaviour is not defined. Nonetheless there is a test case for this - the test doesn't specify the expected behaviour, but it tests that the DUT is not broken afterwards and will behave correctly for subsequent packets.
Because OpenTitan/Mocha's prim_assert.sv disables assertions for Verilator, this test always passes.
If you manually enable assertions, the test occasionally fails.
This is because there is an AXI Stream driven by the TX buffer read output. AXI Streams are forbidden from changing their data while tvalid && !tready, but the data will change if a write occurs to the buffer supplying that data. This is relatively rare.
This is a test issue, not a design issue. We need a way of disabling certain assertions for certain tests.
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with prim_assert.sv, Verilator assertion handling, and the test case for writing to the TX buffer during an active transmission. Trace the AXI Stream read output and the assertion that can fail when TX data changes. Done means selected assertions can be disabled for this test while the DUT’s subsequent-packet behavior remains checked and assertions stay enabled elsewhere.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100