Inconsistent techniques for technology-dependent primitive handling

Nobody has claimed this yet.

Technology-dependent primitives need to be swapped out according to the target (simulation, ASIC, Xilinx FPGA, Altera FPGA). There are three different techniques used in this repo to accomplish this in different places:

1. \`define Macros with \`ifdef statements
2. SystemVerilog parameters with `generate if` blocks
3. FuseSoC virtual cores

(1) is used in `ram_downsizer_w64_r8.sv` and `ram_upsizer_w8_r64.sv`

(2) is used wherever `parameter TARGET` is given, in the MAC and the top level

(3) is used in the rest of the project

The latter is the preferred approach in other lowRISC projects and the least intrusive into the HDL, but implementing it will require some refactoring of legacy MAC code.

Start by comparing ram_downsizer_w64_r8.sv and ram_upsizer_w8_r64.sv with the MAC and top-level locations that use parameter TARGET. Then trace the existing FuseSoC virtual cores and how the legacy MAC code selects technology-dependent primitives. Done means the project consistently uses the preferred virtual-core approach for simulation, ASIC, Xilinx FPGA, and Altera FPGA targets.

Written by the indexing model from the issue text.