llvm/circt

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Circuit IR Compilers and Tools

Stars: 2.2k
Forks: 524
Open beginner issues: 2
Indexed issues: 868
Avg merge: 3d 2h
Merged PRs (30d): 46

Dominant language: C++
License: No license data
Last GitHub push: Sep 18, 2026
Latest indexed: Sep 19, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: good first issue help wanted

Beginner friendly Everything

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868 open issues indexed

[SV][ExportVerilog] Determine `sv.package` ordering via dependence analysis Open

ExportVerilog SV

Difficulty 4/5 3-5 days Newbie friendliness 45/100

llvm/circt#11139 · Opened Sep 18, 2026
[ImportVerilog] String casts to packed byte arrays fail Open

Difficulty 3/5 1-2 days Newbie friendliness 68/100

llvm/circt#11133 · Opened Sep 16, 2026
[ImportVerilog] Support concurrent cover property and cover sequence statements Open

Difficulty 3/5 1-2 days Newbie friendliness 45/100

llvm/circt#11128 · Opened Sep 16, 2026
[ImportVerilog] Support assignment patterns as assignment destinations Open

Difficulty 4/5 3-5 days Newbie friendliness 55/100

llvm/circt#11123 · Opened Sep 15, 2026
[ImportVerilog] Resolve hierarchical outputs from expanded interfaces Open

Difficulty 4/5 3-5 days Newbie friendliness 55/100

llvm/circt#11122 · Opened Sep 15, 2026
[ImportVerilog] Support connected interface-array ports Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

llvm/circt#11121 · Opened Sep 15, 2026
[HW][ExportVerilog] Union Bitcast Layout: Left or Right Jusitfied Open

Difficulty 5/5 Over a week Newbie friendliness 38/100

llvm/circt#11120 · 2 comments · Opened Sep 15, 2026
[FIRRTL] User assertions reading ports produce SV reading values from equivalent wire not port; no mechanism to express intent Open

FIRRTL

Difficulty 5/5 Over a week Newbie friendliness 30/100

llvm/circt#11114 · Opened Sep 14, 2026
[CalyxToHW] Fails to lower 1D calyx.seq_mem to HW: "couldn't convert to core primitive" / "incorrect number of address ports" Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#11111 · 2 comments · Opened Sep 12, 2026
[circt-verilog][RegOfVecToMem] Fail to recognize SRAM with mask Open

llvm/circt#11097 · 3 comments · 1 assignee · Opened Sep 10, 2026
[FIRRTL] some zero-width types fail ExportToVerilog pass w/ out optimizations Open

Difficulty 3/5 1-2 days Newbie friendliness 68/100

llvm/circt#11091 · Opened Sep 9, 2026
[lower-calyx-to-hw] Segmentation fault when calyx.invoke refCellsMap points to local instances instead of ref cells Open

Difficulty 3/5 1-2 days Newbie friendliness 68/100

llvm/circt#11087 · Opened Sep 8, 2026
[FIRRTL] CheckCombLoops crashes on a forceable register reference cast to a layer-colored RWProbe Open

Difficulty 3/5 1-2 days Newbie friendliness 74/100

llvm/circt#11085 · Opened Sep 8, 2026
[SV] Rename "sym_name" in GenerateOp to something different Open

Difficulty 2/5 1-3 hours Newbie friendliness 68/100

llvm/circt#11079 · Opened Sep 3, 2026
[FIRRTL] SizeOf intrinsic requires optimizations enabled to successfully lower Open

FIRRTL

Difficulty 3/5 1-2 days Newbie friendliness 65/100

llvm/circt#11064 · 1 comment · Opened Aug 29, 2026
[FIRRTL] zero-width aggregate consumers crash or produce invalid IR Open

FIRRTL

Difficulty 3/5 1-2 days Newbie friendliness 72/100

llvm/circt#11063 · Opened Aug 28, 2026
[ImportVerilog] Streaming operators fail on unpacked arrays Open

good first issue ImportVerilog

Difficulty 3/5 1-2 days Newbie friendliness 70/100

llvm/circt#11028 · 6 comments · Opened Aug 19, 2026
[Moore] Missing conversions to open array types Open

good first issue Moore

llvm/circt#11027 · 4 comments · 1 assignee · Opened Aug 19, 2026
[ImportVerilog] Don't convert lvalues Open

ImportVerilog

Difficulty 4/5 3-5 days Newbie friendliness 55/100

llvm/circt#11026 · Opened Aug 19, 2026
[MooreToCore] DPI calls with open array arguments are broken Open

good first issue Moore

llvm/circt#11025 · 1 comment · 1 assignee · Opened Aug 19, 2026
[FIRRTL] Connects accepted due to `emitConnect`, but illegal in MLIR Open

bug FIRRTL

Difficulty 5/5 Over a week Newbie friendliness 35/100

llvm/circt#10989 · 2 comments · 4 reactions · Opened Aug 14, 2026
[HWToLLVM] [LLHD] [Arc] Empty coroutine lowering Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#10982 · 1 comment · Opened Aug 12, 2026
[FIRRTL] Lower Classes Assertion Firing Open

bug FIRRTL

Difficulty 3/5 1-2 days Newbie friendliness 55/100

llvm/circt#10959 · Opened Aug 7, 2026
[Arcilator] Define the long-term strategy for FIRRTL probes and sv.xmr.ref Open

Arc Simulator

Difficulty 5/5 Over a week Newbie friendliness 25/100

llvm/circt#10946 · 2 comments · Opened Aug 5, 2026
[FIRRTL][circt-reduce] Improve Instance Externalizer for Domains Open

FIRRTL Reducer

Difficulty 4/5 3-5 days Newbie friendliness 45/100

llvm/circt#10925 · Opened Jul 31, 2026
[crict-verilog][Mem2Reg] Lowering for `llhd.combinational` with peculiar CFG Open

LLHD

Difficulty 4/5 3-5 days Newbie friendliness 45/100

llvm/circt#10912 · 7 comments · Opened Jul 28, 2026
[circt-bmc][LTLToCore] verif.assert on !ltl.property fails to legalize Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#10907 · Opened Jul 27, 2026
[FIRRTL] InferDomain could create ill-formed IR for instance choice Open

Difficulty 4/5 3-5 days Newbie friendliness 38/100

llvm/circt#10903 · 1 comment · Opened Jul 24, 2026
[circt-verilog] Assertion failure in virtual void mlir::RewriterBase::eraseOp(mlir::Operation*) Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#10877 · 2 comments · Opened Jul 21, 2026
[DapathToComb] Assertion failure in singed booth lowering. Open

Difficulty 3/5 1-2 days Newbie friendliness 76/100

llvm/circt#10875 · 3 comments · Opened Jul 21, 2026
[FIRRTL] Improve Domain Errors v2 Open

FIRRTL

Difficulty 5/5 Over a week Newbie friendliness 25/100

llvm/circt#10869 · Opened Jul 20, 2026
[FIRRTL][Inliner] Hierpath's used by non-NLA's are not handled well Open

bug FIRRTL

Difficulty 5/5 Over a week Newbie friendliness 35/100

llvm/circt#10798 · 3 comments · Opened Jul 8, 2026
[circt-verilog][arcilator] End-to-end simulation mismatch on mixed clock/data signals Open

Arc ImportVerilog

Difficulty 4/5 3-5 days Newbie friendliness 35/100

llvm/circt#10797 · Opened Jul 8, 2026
[FIRRTL][canonicalize] FIRRTL canonicalize can create invalid const result types for cat/pad folds Open

Difficulty 3/5 1-2 days Newbie friendliness 74/100

llvm/circt#10787 · Opened Jul 7, 2026
[circt-bmc] `verif.assume` constraints on past timesteps are dropped by per-cycle pop Open

bug verif

llvm/circt#10770 · 2 comments · 1 assignee · Opened Jul 5, 2026
[FIRRTL] Support Aliasing in InferDomains Open

enhancement FIRRTL

Difficulty 5/5 Over a week Newbie friendliness 35/100

llvm/circt#10755 · Opened Jul 2, 2026
[FIRRTL][EliminateWires] rwprobe op is not dominated by target Open

bug FIRRTL

Difficulty 4/5 3-5 days Newbie friendliness 45/100

llvm/circt#10751 · Opened Jul 1, 2026
[Synth] Use LinearTimingArcAttr sensitivity in TechMappper Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#10732 · Opened Jun 25, 2026
[ImportVerilog] DefParam type mismatch after Slang bump Open

ImportVerilog

llvm/circt#10668 · 1 comment · 1 assignee · Opened Jun 16, 2026
[HWAggregateToComb] Mux of unions Open

Difficulty 3/5 1-2 days Newbie friendliness 66/100

llvm/circt#10571 · 2 comments · Opened Jun 1, 2026
[FIRRTL] Question about different Annotation handling between SFC and firtool at Inline phase Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

llvm/circt#10494 · 3 comments · Opened May 18, 2026
[SimToSV][HWToSV] Print-like SV operations are not guarded from synthesis Open

Difficulty 4/5 3-5 days Newbie friendliness 55/100

llvm/circt#10489 · 5 comments · Opened May 16, 2026
[Synth] Add an operation for declarative Cut rewrite pattern Open

Difficulty 5/5 Over a week Newbie friendliness 35/100

llvm/circt#10485 · 1 reaction · Opened May 16, 2026
Feature request: add UDP support Open

Difficulty 5/5 Over a week Newbie friendliness 42/100

llvm/circt#10477 · Opened May 15, 2026
[Synth] Enhance 3-input logic operations Open

llvm/circt#10407 · 2 comments · 1 assignee · Opened May 7, 2026
[FIRRTL][InferResets] Disallow external modules on InstanceChoice? Open

Difficulty 4/5 3-5 days Newbie friendliness 45/100

llvm/circt#10406 · 1 comment · Opened May 7, 2026
[Synth] Enhance 3-input logic gate Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#10405 · Opened May 7, 2026
[Syunth] Enhance 3-input logic gate Open

Difficulty 4/5 3-5 days Newbie friendliness 45/100

llvm/circt#10404 · Opened May 7, 2026
[Synth] Add attribute for linear delay model and pass to approximate them from NLDM attr Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

llvm/circt#10382 · 2 comments · Opened May 5, 2026
[ExportVerilog] Add option to limit identifier length Open

ExportVerilog

Difficulty 3/5 1-2 days Newbie friendliness 55/100

llvm/circt#10356 · 4 comments · Opened Apr 29, 2026

llvm/circt

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