[ImportVerilog] Support connected interface-array ports

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## Problem

ImportVerilog does not correctly handle connected arrays of SystemVerilog interfaces. Interface port lowering assumes a scalar interface instance rather than traversing the connected array and wiring each element's members.

## Reproducer

```systemverilog
interface bus;
logic valid;
logic ready;
modport sink(input valid, output ready);
endinterface

module child(bus.sink b[2], output logic [1:0] q);
assign q = {b[1].valid, b[0].valid};
assign b[0].ready = b[1].valid;
assign b[1].ready = b[0].valid;
endmodule

module top(input logic v0, v1, output logic [1:0] q);
bus b[2]();
assign b[0].valid = v0;
assign b[1].valid = v1;
child c(.b, .q);
endmodule
```

```sh
circt-verilog --ir-moore --top=top repro.sv
```

## Expected behavior

Import succeeds. Each interface element has separate flattened ports, and input/output members connect to the corresponding element.

## Current limitation

The scalar-only connection handling cannot correctly lower this interface-array connection. Related cases include forwarding arrays through modules, arrays without modports, and multidimensional arrays with non-zero or reversed bounds.

Fix proposed in #11117, with regression coverage in `test/Conversion/ImportVerilog/interface-array-port.sv`.

---

AI disclosure: This issue was drafted with assistance from OpenAI Codex.

Start with the reproducer and run circt-verilog --ir-moore --top=top repro.sv to observe the import failure. Read test/Conversion/ImportVerilog/interface-array-port.sv and review the proposed fix in #11117; done means the reproducer imports successfully and regression coverage verifies separate connections for each interface-array element.

Written by the indexing model from the issue text.