Feature request: add UDP support

Nobody has claimed this yet.

Support for SystemVerilog User-Defined Primitives (UDPs) is currently missing in CIRCT. Although obsolete for frontend RTL design, UDPs are still ubiquitous in gate-level netlists and foundry-provided simulation models.

Adding UDP support will significantly broaden CIRCT's real-world applicability in the following scenarios:
1. **Gate-Level Netlist Processing:** Allows frontends (like Moore or slang-based parsers) to successfully ingest and lower post-synthesis netlists without choking on primitive definitions.
2. **ASIC-to-FPGA Prototyping:** Facilitates the translation, mapping, or black-boxing of ASIC cell library models containing combinational/sequential UDP tables into FPGA-compatible IR.
3. **Ecosystem Interoperability:** Enhances CIRCT's readiness for formal verification and physical design automation tools that interact directly with commercial PDKs.

I'd like to work on this if possible.

The issue names Moore and slang-based parsers as relevant frontends; start by tracing how existing primitive definitions are parsed and lowered in those paths. Completion should cover SystemVerilog UDP definitions, including combinational and sequential tables, for the gate-level and simulation-model scenarios described.

Written by the indexing model from the issue text.