[ExportVerilog] Add option to limit identifier length
Open
ExportVerilog
- Dominant language
- C++
- Stars
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- Forks
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- Avg merge
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- Merged PRs (30d)
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Description
Some frontends emit reaaaaaaaally long identifiers. Not a problem for CIRCT but some EDA tools (*cough* *cough* Quartus) choke on those long identifiers. We should add an option to limit the number of characters in identifiers we emit to verilog to `N`.
Contributor guide
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Research direction
Start by locating the ExportVerilog entry point and the code that emits identifiers. Trace how an option is defined and passed into identifier emission, then verify that generated Verilog identifiers are limited to N characters using the existing ExportVerilog tests or an appropriate focused test.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 55/100