[FIRRTL] some zero-width types fail ExportToVerilog pass w/ out optimizations

Nobody has claimed this yet.

When certain zero-width types exist but optimizations are disabled, the passes that are meant to remove them do not seem to run, causing a failure when exporting to verilog. Based on my testing, this seems to only happen with nested arrays of length zero? But I'll look more into it tomorrow and see if I can figure out a fix.

```firrtl
FIRRTL version 4.0.0
circuit Top:
public module Top:
output size: UInt<32>
wire empty: {nested: UInt<1>[0]} ; (FAILS)
; wire empty: UInt<0>[2] ; (WORKS)
; wire empty: UInt<1>[0] ; (WORKS)
; wire empty: {nested: UInt<0>} ; (WORKS)
invalidate empty
node sizeNode = intrinsic(circt_sizeof : UInt<32>, empty)
connect size, sizeNode
```

```
Assertion failed: (!isZeroBitType(op.getType()) && "zero-bit types not allowed at this point"), function visitTypeOp, file ExportVerilog.cpp, line 3133.
```

Reproduce the failure with the FIRRTL 4.0.0 snippet and optimizations disabled. Start at ExportVerilog.cpp line 3133 and trace the zero-width-type removal passes for nested zero-length arrays. Done means the example exports to Verilog without the assertion while the existing working cases remain valid.

Written by the indexing model from the issue text.