[Synth] Enhance 3-input logic gate

Look at https://si2.epfl.ch/~demichel/publications/archive/2021/3Input.pdf and introduce a few operations that would be benefitial target of exact synthesis.
```
synth.onehot (n-input)
synth.mux _inv (3-input + per-input inverter)
synth.majority (2*n+1 input, 3, 5,..) Note that this is re-introduction of synth.mig.maj_inv. This time majority operation is not framed as a primary target of homogeneous logic representation.
```

Read the linked 3-input logic-gate paper, then inspect the existing synth.mig.maj_inv operation and related exact-synthesis targets. Determine how synth.onehot, synth.mux with per-input inversion, and variable-input synth.majority should be represented; done means these operations are available as exact-synthesis targets for their stated input sizes.

Written by the indexing model from the issue text.