chipsalliance/python-fpga-interchange

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Python interface to FPGA interchange format

Stars: 41
Forks: 12
Open beginner issues: 0
Indexed issues: 19

Dominant language: Python
License: ISC
Last GitHub push: Oct 19, 2022
Latest indexed: Sep 15, 2026
Contributing guide: No contributing guide
Code of conduct: Code of conduct
Beginner labels: No beginner labels indexed
PR merge metrics: No merged PRs in 30d

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19 open issues indexed

Need canonical storage solution to ensure binary consistency Open

chipsalliance/python-fpga-interchange#8 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Remove rapidyaml git+https in requirements once rapidyaml is in PyPi Open

chipsalliance/python-fpga-interchange#11 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add XML support to plaintext FPGA interchange Open

chipsalliance/python-fpga-interchange#29 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Improve YAML anchor names Open

enhancement

chipsalliance/python-fpga-interchange#30 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Optimize node and pip walking Open

chipsalliance/python-fpga-interchange#31 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Requiring a NULL tile at (0, 0) is Xilinx-specific Open

chipsalliance/python-fpga-interchange#34 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Setup automatic publishing packages to PyPI Open

chipsalliance/python-fpga-interchange#35 · 2 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Replace local license checks with the SymbiFlow/actions/checks@main action Open

chipsalliance/python-fpga-interchange#59 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Invalid DCP when the BUFG route-thru is used Open

chipsalliance/python-fpga-interchange#61 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Cleaner nextpnr BBA generation Open

enhancement

chipsalliance/python-fpga-interchange#66 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add FASM generator testing Open

chipsalliance/python-fpga-interchange#79 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Allow patching of StringIdx values Open

enhancement

chipsalliance/python-fpga-interchange#81 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Allow patching of lists Open

chipsalliance/python-fpga-interchange#82 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add support to emit VTR XML architecture file Open

chipsalliance/python-fpga-interchange#101 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
XDC constraints attributes on cells/ports missing from the netlists Open

chipsalliance/python-fpga-interchange#109 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Issues trying to create YAML device file from example Open

chipsalliance/python-fpga-interchange#117 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
FASM generators: add LUTRAM support for xc7 Open

chipsalliance/python-fpga-interchange#128 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
AttributeError when converts IF to json Open

chipsalliance/python-fpga-interchange#162 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
VPR generates warnings about missing timing in testarch Open

chipsalliance/python-fpga-interchange#166 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

chipsalliance/python-fpga-interchange

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