chipsalliance / chipsalliance/python-fpga-interchange
Requiring a NULL tile at (0, 0) is Xilinx-specific
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- Python
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Description
https://github.com/SymbiFlow/python-fpga-interchange/blob/master/fpga_interchange/populate_chip_info.py#L1139 assumes that the tile at (0, 0) is NULL.
This works for Xilinx, and can be made to work for Nexus by renaming that tile (because it's equivalent to a NULL tile) but this should be made generic in the future.
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