chipsalliance / chipsalliance/python-fpga-interchange
Optimize node and pip walking
- Dominant language
- Python
- Stars
- 41
- Forks
- 12
- PR merge metrics
- No merged PRs in 30d
Description
Currently both node and pip walks could use some optimization.
Effectively `getPipsDownhill` is implemented as:
```
# For each wire in node
for(wire : node.wires):
# For each pip in wire
for(pip : wire.downhill_pips):
yield pip
```
For longer nodes, several of those wire lookups simply say "no pips here". The node could be implemented where wires with pips are sorted before wires without pips, and the outside loop could be terminated if there are no more pips in the node. Unclear the benefit of this change, especially relative to a graph folding solution (e.g. https://github.com/SymbiFlow/RapidWright/issues/1) which could be more efficient here.
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