XDC constraints attributes on cells/ports missing from the netlists

While dealing with https://github.com/SymbiFlow/python-fpga-interchange/pull/108 I have bumped into one issue which has many ways of being solved IMO.

The problem is that the XDC constraints that add attributes do not reflect outside of nextpnr, as the XDC parser is embedded within. This means that the logical netlist won't have information, for instance, on the IOSTANDARD attribute of a pad, unless this is specified in the design.

The attributes are quite important when, for instance, writing the FASM features.

Some of the possible solutions:
1. enhance the physical netlist schema to include information on additional attributes assigned to the cells during p&r (e.g. when reading the XDCs)
1. read the XDC file once again alongside with logical and physical netlists
1. add the attributes when generating the logical netlist and read the XDC at that step