aws/aws-fpga

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Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Stars: 1.7k
Forks: 538
Open beginner issues: 0
Indexed issues: 42

Dominant language: SystemVerilog
License: No license data
Last GitHub push: Aug 6, 2026
Latest indexed: Sep 14, 2026
Contributing guide: Contributing guide
Code of conduct: Code of conduct
Beginner labels: No beginner labels indexed
PR merge metrics: No merged PRs in 30d

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42 open issues indexed

AHB Slave interface issue in Vivado IP (AWS f1 Instance) Open

aws/aws-fpga#603 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
vitis_setup.sh with non-root permissions Open

aws/aws-fpga#618 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Accessing the AXI-Lite via the fpga_pci_attach call... Open

aws/aws-fpga#640 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Debug embedded microblaze using XVC JTAG in AWS FPGA shell Open

aws/aws-fpga#641 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Instance status checks failures Open

aws/aws-fpga#642 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Connect MicroBlaze Debug Module (MDM) to Virtual JTAG in Vivado IP Integrator Open

aws/aws-fpga#644 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Does AWS F1 support Vitis AI 2.5? Open

aws/aws-fpga#646 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Loading of simulation waveform in Vivado is too slow Open

aws/aws-fpga#650 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
When running with F1.16xlarge on all FPGAs, PCIE access to one of them is stuck Open

aws/aws-fpga#656 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Compatibility of U200-Designed xclbin / create_vitis_afi.sh with AWS F1 Instance and XRT API Usage Open

aws/aws-fpga#657 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Inquiry About FPGA Developer AMI Support and Future Updates Open

aws/aws-fpga#658 · 17 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
F2 XDMA shell availability Open

aws/aws-fpga#671 · 14 comments · 2 reactions · 0 assignees · Indexed Sep 14, 2026
Could NOT find Vitis (missing: Vitis_AIE_INCLUDE_DIR) Open

aws/aws-fpga#677 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Unable to access the instance from India Open

aws/aws-fpga#679 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Unable to setup a custom CL on F2 instance FPGA and run it through my host script Open

aws/aws-fpga#685 · 22 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Hierarchal Synthesis on Vivado Open

aws/aws-fpga#701 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Missing cl_sh_id0/1 causing bitstream config to fail Open

aws/aws-fpga#703 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Couple AFI to an AMI on the Marketplace Open

aws/aws-fpga#712 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Vitis AFI creation on F2 instance Open

aws/aws-fpga#713 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Want to create simple CL on F2, but running into significant issues Open

aws/aws-fpga#723 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
ENA to FPGA PCIe P2P networking feature? Open

aws/aws-fpga#725 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
How to access (Read/Write) DDR from AWS Shell Open

aws/aws-fpga#732 · 25 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Read Write From DDR in F1 instance Open

aws/aws-fpga#734 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
XVC PCIE Binary Fails to Connect to device Open

aws/aws-fpga#739 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
should we ignore this message?: "WARNING: [Route ...] Router estimated timing not met." Open

aws/aws-fpga#740 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
cl_dram_hbm_dma builds but running the way the tutorial says produces "unable to open read dma queue" Open

aws/aws-fpga#744 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
vivado gives opaque error messages: "ERROR: [Synth 8-5809] Error generated from encrypted envelope." Open

aws/aws-fpga#745 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Tcl glob expression for .v and .sv files is broken: should be *.{s,}v Open

aws/aws-fpga#746 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
generate_sim_file_list.py excludes .svh and .vh files Open

aws/aws-fpga#754 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
cl_peek and cl_poke usage Open

aws/aws-fpga#755 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
vivado 2025.2 support Open

aws/aws-fpga#758 · 5 comments · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Documentation on clock tools seems to be inconsistent. Open

aws/aws-fpga#760 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Inconsistent "F2 Clock Recipe Tables" Open

aws/aws-fpga#761 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
How are we supposed to set the clock and timing constraints? We provide a detailed example worked out that contradicts the documentation and fails to allow configuring the clock and timing. Open

aws/aws-fpga#763 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Support for Vitis AFI flow (`create_vitis_afi.sh`) on F2 instances for new projects Open

aws/aws-fpga#765 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Add Riviera-PRO support Open

aws/aws-fpga#770 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
support for multiple queues in SPP driver Open

aws/aws-fpga#778 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 14, 2026
C_TEST not working Open

aws/aws-fpga#781 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Question: XDMA Driver Install Guide vs ERRATA Open

aws/aws-fpga#790 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
AWS F2 FPGA to FPGA low latency communication Open

aws/aws-fpga#791 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
AWS F2 Vitis platform mismatch: device shell v10212415 but public platforms are v10162423/v03072517 Open

aws/aws-fpga#795 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
F2 small shell: place_design (Vivado 2025.2) drops a physical-only VCC tie on two locked static slices at ~1.3M-cell CL scale -> HDPRVerify-41, AFI ingestion rejected (deterministic, scale-triggered) Open

aws/aws-fpga#799 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026

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