Hierarchal Synthesis on Vivado
Open
- Dominant language
- SystemVerilog
- Stars
- 1.7k
- Forks
- 538
- PR merge metrics
- No merged PRs in 30d
Description
How can I set reference to the checkpoint of pre-synthesized submodule while running the top level synthesis in order to save run-time. Are there any example scripts which I can refer to?
Contributor guide
Research direction
The issue names no files, tests, or entry points. Start by locating the Vivado hierarchical-synthesis guidance and checkpoint example scripts in the repository; done would be a clear, runnable example showing how to reuse a pre-synthesized submodule checkpoint during top-level synthesis.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Documentation
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100