AWS F2 FPGA to FPGA low latency communication
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- SystemVerilog
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Description
Hello,
Based on my research and this thread -> https://repost.aws/questions/QUxDMcF1IKRTq5haqCzEUlsA/f2-pcie-peer-to-peer-fpga-fpga-connectivity
it seems like the F2 instances do not support direct Peer to Peer PCIe for FPGA to FPGA communication, like F1 instances did ??
In other threads the advice was to use DPDK - but to my understanding DPDK would go through userspace / host - and thus would incur latency.
Our design needs the lowest possible latency for inter FPGA communication. What would be the best way to achieve this?
Are there any code examples out there that we can follow or any documentation for what latency we can expect using DPDK ?
thanks.
Contributor guide
Research direction
The issue names AWS F2 instances, FPGA-to-FPGA PCIe peer-to-peer communication, and DPDK, but no repository file, test, or entry point. Start by reading the linked AWS discussion and the repository's F2 and networking documentation; done would require a confirmed supported approach, relevant examples, and documented latency expectations.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- aws
- Domain
- cloud, embedded-iot, networking
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 30/100