aws / aws/aws-fpga

generate_sim_file_list.py excludes .svh and .vh files

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SystemVerilog
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Description

In hdk/common/verif/scripts/generate_sim_file_list.py, at line 48:
` if not file_path.endswith('h') and not file_path.endswith('md'):
`
` generated_file_list.append(file_path.replace(cl_dir, '$CL_DIR'))
`
As .svh and .vh files end with 'h', they are excluded from the simulation compile list top.[sim].f, and can cause sims with .svh/.sh files to not build.

Contributor guide

Open the contributing guide

Research direction

Read hdk/common/verif/scripts/generate_sim_file_list.py at line 48 and trace how its output becomes top.[sim].f. Confirm that .svh and .vh files are included in the generated simulation compile list without changing the handling of the other extensions, then verify the resulting list.

Written by the indexing model from the issue text.

Assessment

Tech stack
python
Domain
build-system
Issue type
Bug
Difficulty
1/5
Estimated time
Under an hour
Activity status
Stale
Clarity
Clearly specified
Newbie friendliness
55/100

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