Loading of simulation waveform in Vivado is too slow
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- SystemVerilog
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Description
Hi,
I have been running a simulation in Vivado. Writing into the BRAM of 16 KB through PCIS is taking more than 2 hours. I need to write more than 10 BRAMS. If it takes time like this, I am worrying that I need to wait more than a day to simulate my design.
Is it expected behaviour?
Is there any way to reduce the simulation time?
Regards
Gogul
Contributor guide
Research direction
Start by reproducing the Vivado simulation that writes 16 KB BRAM blocks through PCIS, measuring the waveform-loading and write time. There are no files or tests named in the issue; done would be determining whether the delay is expected and documenting a validated way to reduce simulation time, if one exists.
Written by the indexing model from the issue text.
Assessment
- Domain
- performance
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100