Missing cl_sh_id0/1 causing bitstream config to fail

I have a design that I was able to successfully generate a bitstream for, but when I tried to load the AFI onto the FPGA it would say loaded and then immediately go back to cleared. The tools didn't give me any error messages of any kind and nothing could be found in the log files either.

It turned out that I forgot to export cl_sh_id0/1:

> + assign cl_sh_id0[31:0] = `CL_SH_ID0;
> + assign cl_sh_id1[31:0] = `CL_SH_ID1;

Would it be possible to add a check in the hdk scripts to catch this before synthesis happens and let the user know? This was extremely difficult to debug because there was no way of knowing why the device just aborted and dumped the bitstream. It could be an issue with the design, e.g.., power, multi-driven nets, floating pins, etc... causing config to fail. Please consider adding this.

Start with the HDK scripts that run before synthesis and trace where design-level validation occurs. Add a check for the required cl_sh_id0 and cl_sh_id1 exports, with an actionable error before synthesis; verify that designs missing them are rejected while designs containing the assignments proceed.

Written by the indexing model from the issue text.