intel/llvm

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Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.

Stars: 1.5k
Forks: 854
Open beginner issues: 1
Indexed issues: 662
Avg merge: 3d 17h
Merged PRs (30d): 137

Dominant language: LLVM
License: No license data
Last GitHub push: Sep 15, 2026
Latest indexed: Sep 17, 2026
Contributing guide: Contributing guide
Code of conduct: Code of conduct
Beginner labels: help wanted good first issue

Open All

659 open issues indexed

[SYCL] Enqueuing USM memory free Open

confirmed enhancement spec extension

intel/llvm#6350 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
CTAD bug in vector length Open

bug confirmed

intel/llvm#6402 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[HIP] Compiling code for different AMD architectures Open

enhancement hip

intel/llvm#6412 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Assert/assert_in_simultaneously_multiple_tus.cpp randomly failing on CUDA Open

bug cuda runtime

intel/llvm#8800 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Sporadic llvm-test-suite failures on CUDA back-end. Open

cuda runtime

intel/llvm#6463 · 7 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
[CUDA] llvm-test-suite `Basic/image/image_write_fp16.cpp` failure Open

bug cuda runtime

intel/llvm#6491 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Linker issue with libclang_rt.builtins.a Open

hip

intel/llvm#6513 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
can we use time difference between two events? Open

bug confirmed

intel/llvm#6514 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Investigate flaky assert tests for HIP Open

bug hip

intel/llvm#6520 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Sporadic llvm-test-suite failures on HIP back-end Open

bug hip

intel/llvm#6633 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Handling of Builtin Variables violates OpenCL 3.0 SPIR-V Environment Specification. Open

bug confirmed SPIR-V

intel/llvm#6703 · 9 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Rename intel_reqd_group_size metadata Open

compiler confirmed

intel/llvm#6824 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
NVIDIA CUDA GPU programming — processing 8 BILLION hashes/sec on V100s Open

cuda enhancement

intel/llvm#6943 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][XPTI] Memory Transfer event instrumentation Open

bug confirmed

intel/llvm#6972 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
SYCL/Basic/event_profiling_info.cpp flakily failing on CUDA/HIP Open

bug cuda hip runtime

intel/llvm#8799 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Compiler assets missing for public release 2022-06 Open

confirmed enhancement

intel/llvm#7000 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL] Please stop using global destructors. Open

confirmed enhancement

intel/llvm#7020 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Wrong code generation in optimization mode. Open

bug confirmed

intel/llvm#7230 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Out of date SYCL_RT_WARNING_LEVEL documentation Open

bug confirmed Documentation

intel/llvm#7248 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
`cgeist` always represents Boolean values using `i8` Open

bug sycl-mlir

intel/llvm#7314 · 2 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
`cgeist` crashes when dealing with overloaded operators Open

bug sycl-mlir

intel/llvm#7316 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
[SYCL-MLIR] Use `VectorType` for different vector types Open

enhancement sycl-mlir

intel/llvm#7356 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][CUDA] Build failed with fatal error "error in backend: Undefined external symbol "exp"" Open

bug cuda

intel/llvm#7386 · 10 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Implement new `polygeist.memrefdiff` operation Open

enhancement sycl-mlir

intel/llvm#7431 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 17, 2026
[SYCL-MLIR] Missing SYCL types Open

enhancement sycl-mlir

intel/llvm#7537 · 1 comment · 0 reactions · 5 assignees · Indexed Sep 17, 2026
Broken section links in environment variables generated documentation Open

bug confirmed Documentation

intel/llvm#7539 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
sycl::is_compatible is currently not very useful Open

bug confirmed

intel/llvm#7561 · 6 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
[SYCL-MLIR] Improve SYCL test suite success rate Open

enhancement sycl-mlir

intel/llvm#7585 · 25 comments · 0 reactions · 3 assignees · Indexed Sep 17, 2026
Track all customizations that are made in llvm-spirv in intel/llvm Open

confirmed enhancement SPIR-V

intel/llvm#7592 · 14 comments · 0 reactions · 2 assignees · Indexed Sep 17, 2026
Support for complex data types and functions in SYCL running on NVIDIA Open

cuda enhancement

intel/llvm#7611 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Fragile ABI checks Open

bug confirmed

intel/llvm#7620 · 2 comments · 2 reactions · 0 assignees · Indexed Sep 17, 2026
in-kernel dynamic memory allocation Open

confirmed enhancement

intel/llvm#7623 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][CUDA] migrate cublasLt functions Open

cuda enhancement

intel/llvm#7624 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][HIP] Unresolved Assert/.* tests failures Open

bug cuda hip

intel/llvm#7634 · 17 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL-MLIR][RODINIA]: Rodinia performance benchmarks for SYCL Open

enhancement sycl-mlir

intel/llvm#7641 · 23 comments · 0 reactions · 3 assignees · Indexed Sep 17, 2026
check_error not handle CUDA_ERROR_DEINITIALIZED? Open

bug cuda

intel/llvm#7654 · 2 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
[SYCL] `ONEAPI_DEVICE_SELECTOR` does not really select anything and should be renamed to fit the semantics Open

enhancement

intel/llvm#7666 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Exploit SPIRV target transform information for SPIR triple. Open

compiler confirmed enhancement

intel/llvm#7670 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Add SYCL extension specification for max_work_group_size Open

confirmed enhancement

intel/llvm#7700 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Ignore duplicate attribute with SYCLIntelBankBitsAttr Open

bug confirmed

intel/llvm#7817 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Compile SYCL code as static portable program Open

enhancement

intel/llvm#7828 · 3 comments · 4 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][XPTI] Several issues in XPTI Open

bug confirmed

intel/llvm#7860 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
Kernel fails to compile for CPU target seemingly due to use of OpBitReverse in SPIR-V Open

bug confirmed OCL CPU Experimental RT SPIR-V

intel/llvm#7868 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL] migrate max grid sizes in CUDA and HIP Open

confirmed enhancement

intel/llvm#7899 · 9 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][L0][CUDA][HIP] L0 plugin enabled for CUDA and HIP backends Open

bug confirmed good first issue python

intel/llvm#7976 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
[SYCL][HIP] Support for inclusive, exclusive scan over group SYCL 2020 Open

enhancement hip

intel/llvm#7987 · 0 comments · 1 reaction · 0 assignees · Indexed Sep 17, 2026
Remove the NEAT dependency of OpenCL CPU test and revert #7979 Open

confirmed enhancement

intel/llvm#7988 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
hipErrorNoBinaryForGpu: Unable to find code object for all current devices? Open

bug hip

intel/llvm#7993 · 18 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026
Generate different types for scalar and memory values Open

enhancement sycl-mlir

intel/llvm#7994 · 2 comments · 0 reactions · 1 assignee · Indexed Sep 17, 2026
[SYCL] migrate max threads per multiprocessor in CUDA and HIP Open

cuda enhancement hip

intel/llvm#7997 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 17, 2026

intel/llvm

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