[HIP] Compiling code for different AMD architectures
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enhancement
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- LLVM
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Description
DPC++ with HIP AMD backend requires to specify a target architecture via `-Xsycl-target-backend --offload-arch=gfx90a`.
This means that the code should be compiled for each architecture which may be a problem for libraries that have such code.
Is it possible to add support for AMD backend similar to CUDA via `-fsycl-targets=nvptx64-nvidia-cuda`?
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