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lowRISC

35 indexed repositories · View on GitHub

• opentitan

  OpenTitan: Open source silicon root of trust

  SystemVerilog · 3648 stars

• ibex

  Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

  SystemVerilog · 2062 stars

• lowrisc-chip

  The root repo for lowRISC project and FPGA demos.

  SystemVerilog · 601 stars

• style-guides

  lowRISC Style Guides

  541 stars

• riscv-llvm

  RISC-V support for LLVM projects (LLVM, Clang, ...)

  Shell · 277 stars

• muntjac

  64-bit multicore Linux-capable RISC-V processor

  SystemVerilog · 121 stars

• ibex-demo-system

  A demo system for Ibex including debug support and some peripherals

  C · 99 stars

• lowrisc-fpga

  Untethered (stand-alone) FPGA implementation of the lowRISC SoC

  C · 56 stars

• sonata-system

  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI

  C++ · 54 stars

• lowrisc-toolchains

  UNSUPPORTED INTERNAL toolchain builds

  Shell · 49 stars

• ot-sca

  Side-channel analysis setup for OpenTitan

  Jupyter Notebook · 43 stars

• mocha

  CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.

  SystemVerilog · 38 stars

• hjson_to_gantt

  A Python script to generate a Gantt chart from a (H)JSON input

  Python · 34 stars

• riscv-compliance

  TEMPORARY FORK of the riscv-compliance repository

  C · 34 stars

• ethernet

  Open-source memory-mapped Ethernet MAC for FPGA with RGMII interface

  SystemVerilog · 23 stars

• lowrisc-nexys4

  FPGA demo for Digilent NEXYS 4 board

  Tcl · 22 stars

• sunburst-chip

  An open silicon CHERIoT Ibex microcontroller chip

  C · 19 stars

• synfi

  OpenTitan FI formal verification framework

  Python · 18 stars

• ibex-demo-system-labs

  Labs for the Ibex Demo System

  C · 18 stars

• manticore

  Rust · 17 stars

• 15 more repositories live on View on GitHub