[sram] bring the RAM configuration ports out to the axi_sram boundary
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- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
Currently, `axi_sram.sv` instantiates two prim_ram_1p memories but ties off their configuration interfaces (`cfg_i` / `cfg_rsp_o`). These two ports are how the memory macros are configured from the outside, so currently there is no way for anything to configure them once the generics are replaced with real hard macros.
The fix is to add the ports to the block and route them to both rams, like how i2c already does.
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start in axi_sram.sv and inspect the two prim_ram_1p instances, their cfg_i and cfg_rsp_o connections, and the existing i2c pattern mentioned in the issue. Add the configuration ports at the axi_sram boundary and route them to both memories; done means external configuration is available for each instantiated RAM without the ports being tied off.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Active
- Clarity
- Clearly specified
- Newbie friendliness
- 78/100