[prim] Formality encounters syntax errors
- Dominant language
- SystemVerilog
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Description
### Description
**Formality reports a syntax error when reading this line**
https://github.com/lowRISC/opentitan/blob/f49474bc89c3ce8a99536329a1e16bf22936da37/hw/ip/prim/rtl/prim_assert_sec_cm.svh#L115
I believe the reason is that `!rst_ni` is illegal.
I’ve looked into why only this line reports an error. Other assertions use `ASSERT_DEFAULT_RST`, so I think this is a simple oversight. Other tools happen to support this syntax and do not throw errors.
https://github.com/lowRISC/opentitan/blob/f49474bc89c3ce8a99536329a1e16bf22936da37/hw/ip/prim/rtl/prim_assert.sv#L18
https://github.com/lowRISC/opentitan/blob/f49474bc89c3ce8a99536329a1e16bf22936da37/hw/ip/prim/rtl/prim_assert.sv#L119
Give a description of the problem, listing similar issues and if able:
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Contributor guide
Research direction
Start at hw/ip/prim/rtl/prim_assert_sec_cm.svh line 115 and compare the assertion patterns with hw/ip/prim/rtl/prim_assert.sv lines 18 and 119. Use Formality to check the affected assertion and confirm that the syntax error is resolved without introducing failures in the related assertions.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Active
- Clarity
- Clearly specified
- Newbie friendliness
- 82/100