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f4pga

6 indexed repositories · View on GitHub

prjxray
Documenting the Xilinx 7-series bit-stream format.

Python · 914 stars
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Jupyter Notebook · 314 stars
ideas
Random ideas and interesting ideas for things we hope to eventually do.

86 stars
prjuray
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

SystemVerilog · 84 stars
f4pga-website

SCSS · 3 stars
actions
GitHub Actions to be reused in CI workflows

Python · 2 stars

Open All

512 open issues indexed

Remove `assign tx = rx` Open

f4pga/f4pga-arch-defs#658 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[xc7] Determine why cluster pin feasibility filter stopped working after CLB tile split Open

arch-xc7-artix7 bug help wanted

f4pga/f4pga-arch-defs#675 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[xc7] Improve CI runtime Open

arch-xc7-artix7 enhancement good first issue help wanted

f4pga/f4pga-arch-defs#686 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Automated testing on hardware of all distributed RAM types Open

arch-xc7

f4pga/f4pga-arch-defs#687 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make sphinx understand python type hints Open

f4pga/f4pga-arch-defs#689 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make `muxgen.py` support for generating timing information Open

f4pga/f4pga-arch-defs#692 · 0 comments · 0 reactions · 2 assignees · Indexed Sep 15, 2026
Remove `BLK_TL-` prefix from slices names Open

f4pga/f4pga-arch-defs#694 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Rename LUT-RAM stub to something more useful Open

f4pga/f4pga-arch-defs#695 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
cmake doesn't seem to update when environment values change Open

f4pga/f4pga-arch-defs#696 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Fix the clock output detection so that dsp_in_registered test can be enabled Open

f4pga/f4pga-arch-defs#705 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Fix the clock input detection so that dsp_out_registered test can be enabled Open

f4pga/f4pga-arch-defs#706 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Fix the clock input detection so that dsp_partial_registered test can be enabled Open

f4pga/f4pga-arch-defs#707 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Implement block RAM FIFO{18,36}E1 primitives Open

arch-xc7 help wanted

f4pga/f4pga-arch-defs#709 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add ECC support to block RAM Open

arch-xc7 help wanted

f4pga/f4pga-arch-defs#710 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: vlog_to_{pbtype/model} cannot handle cell inputs connected to a site internal constant source (e.g. 0 or 1) Open

f4pga/f4pga-arch-defs#715 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Convert grid functions in utils/vpr_pbtype_arch_wrapper.py to a class Open

f4pga/f4pga-arch-defs#717 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Remove sys.path manipulation in Python code Open

f4pga/f4pga-arch-defs#718 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Update golden targets missing dependencies Open

f4pga/f4pga-arch-defs#719 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Rename golden update targets to be better Open

f4pga/f4pga-arch-defs#720 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Consistently format Verilog modules verse instances Open

f4pga/f4pga-arch-defs#723 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make vpr_pbtype_to_eblif support inbuilt blif model types Open

f4pga/f4pga-arch-defs#725 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Cmake warnings: Open

f4pga/f4pga-arch-defs#736 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add color information to the VPR arch metadata Open

f4pga/f4pga-arch-defs#741 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Use Yosys on .sim.v files to generate a .eblif needed for architecture testing Open

f4pga/f4pga-arch-defs#746 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add v2x to use specify section rather than the extra timing attributes Open

f4pga/f4pga-arch-defs#748 · 4 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Race condition in rr_graph generation for ice40? Open

f4pga/f4pga-arch-defs#750 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Refactor grid_visualizer and get upstream Open

arch-* cleanup enhancement good first issue help wanted lang-python lang-xml type-utils

f4pga/f4pga-arch-defs#752 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
[xc7] Packer inter cluster delay should be seeded from routing data Open

f4pga/f4pga-arch-defs#762 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make v2x support dpram32 generation Open

f4pga/f4pga-arch-defs#776 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
xc7: ntemplate.nlut.sim.v and ntemplate.nlut.pb_type.xml don't match Open

f4pga/f4pga-arch-defs#780 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
V2X incorrectly inserts "combinational_sink_ports" Open

f4pga/f4pga-arch-defs#784 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Modeling the FDCE with timing for VPR Open

f4pga/f4pga-arch-defs#788 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
rewrite utils/python_health_helper.sh in python Open

lang-python type-infra

f4pga/f4pga-arch-defs#791 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Test 32-bit distributed RAM with larger designs Open

f4pga/f4pga-arch-defs#822 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
cmake: xml_lint() is currently broken, doesn't model the target dependency correctly Open

f4pga/f4pga-arch-defs#855 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Old unused files in xc7? Open

f4pga/f4pga-arch-defs#889 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
[xc7] Support RAMB36E1 Open

f4pga/f4pga-arch-defs#902 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
[xc7/fasm2v] Crash when an all-zero initialized LUT is connected to an output pin Open

arch-xc7-artix7 bug lang-verilog

f4pga/f4pga-arch-defs#922 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Look at new `abc_XXX` attributes in Yosys Open

f4pga/f4pga-arch-defs#951 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[xc7] SRL32/SRL16 fix and test routing through DFFMUX.MC31 Open

f4pga/f4pga-arch-defs#974 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Convert to using sdc for Series 7 work Open

f4pga/f4pga-arch-defs#1000 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Resolve TODOs in ilogice3, ologice3, idelaye2 pb_types Open

f4pga/f4pga-arch-defs#1014 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[xc7] Invalid usage of FAN[0-7] or BYP[0-7] nodes Open

arch-artix7 bug

f4pga/f4pga-arch-defs#1019 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[xc7] PADOUT pips are special Open

arch-artix7 bug cleanup

f4pga/f4pga-arch-defs#1033 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Cleanup prjxray_import_tile and company Open

f4pga/f4pga-arch-defs#1089 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Add a simulation model for the PLLE2_ADV Open

f4pga/f4pga-arch-defs#1119 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Math operations on real constants in Yosys Open

f4pga/f4pga-arch-defs#1132 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
cmake setup depends on users Python install Open

f4pga/f4pga-arch-defs#1155 · 9 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create make install target Open

f4pga/f4pga-arch-defs#1160 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Setting bits for IOB tiles not used by a design Open

f4pga/f4pga-arch-defs#1169 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

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