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f4pga

6 indexed repositories · View on GitHub

prjxray
Documenting the Xilinx 7-series bit-stream format.

Python · 914 stars
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Jupyter Notebook · 314 stars
ideas
Random ideas and interesting ideas for things we hope to eventually do.

86 stars
prjuray
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

SystemVerilog · 84 stars
f4pga-website

SCSS · 3 stars
actions
GitHub Actions to be reused in CI workflows

Python · 2 stars

Open All

512 open issues indexed

Consider adding column to pinmap CSV's documenting type of pin Open

good first issue

f4pga/f4pga-arch-defs#224 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Consider adding knowledge of global wires and be able to assign Open

todo :spiral_notepad:

f4pga/f4pga-arch-defs#225 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
DEVICE_TYPE in CMake system is a bad abstraction Open

f4pga/f4pga-arch-defs#234 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Move points.py point bag to tracks to minimize span distance Open

f4pga/f4pga-arch-defs#255 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
cmake: Extract the xsltproc command from DEFINE_DEVICE into xml.cmake Open

good first issue help wanted

f4pga/f4pga-arch-defs#260 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Write up documentation on "project_xray_prepare_database" output Open

f4pga/f4pga-arch-defs#264 · 1 comment · 0 reactions · 2 assignees · Indexed Sep 15, 2026
v2x: Add features to support generation of all series 7 architecture models Open

arch-*

f4pga/f4pga-arch-defs#287 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Improve CMake configuration time Open

arch-* good first issue

f4pga/f4pga-arch-defs#289 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Reduce tech debt in 7-series support Open

arch-xc7

f4pga/f4pga-arch-defs#291 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Generating svg image of xxx.sim.v output for Artix 7 SLICEL is broken Open

arch-xc7 lang-verilog lang-xml type-sim

f4pga/f4pga-arch-defs#305 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Sim models for the ff and 5ff are missing Open

arch-xc7 lang-verilog lang-xml type-sim

f4pga/f4pga-arch-defs#306 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Merge the channel.py and channel2.py files in utils Open

dependencies help wanted lang-python lang-xml type-defs type-utils type-vpr

f4pga/f4pga-arch-defs#338 · 11 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Merge the graph.py and graph2.py files in utils Open

dependencies lang-python lang-xml type-defs type-utils type-vpr

f4pga/f4pga-arch-defs#339 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Enable OpenOCD for Zynq Open

f4pga/f4pga-arch-defs#344 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Debug and enable equivalence tests for Travis Open

help wanted todo :spiral_notepad: type-infra

f4pga/f4pga-arch-defs#356 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Need to handle slice wide inverters in 7-series FF's Open

arch-xc7 bug

f4pga/f4pga-arch-defs#373 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add cmake target for PDF specs extractor Open

enhancement type-build

f4pga/f4pga-arch-defs#376 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
ice40: Implement ColBuf in routing import Open

arch-ice40 enhancement lang-python

f4pga/f4pga-arch-defs#464 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
ice40: handle IO params in synthesis step Open

arch-ice40 lang-verilog lang-xml type-defs type-vpr

f4pga/f4pga-arch-defs#465 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add unit testing for FASM support Open

lang-python lang-xml type-vpr

f4pga/f4pga-arch-defs#467 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Always PPIPs should be modelled as shorts Open

arch-xc7 bug

f4pga/f4pga-arch-defs#524 · 3 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Remove use of add_test in cmake files as it doesn't have dependency support Open

f4pga/f4pga-arch-defs#526 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Improve 7-series test coverage Open

arch-xc7 help wanted

f4pga/f4pga-arch-defs#527 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
clean up `utils` modules with best practices and consistent style Open

lang-python

f4pga/f4pga-arch-defs#528 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Add documentation to specialize_carrychains.py Open

f4pga/f4pga-arch-defs#532 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
report code coverage for tests Open

f4pga/f4pga-arch-defs#536 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
[XC7] Remove logic to disable global constant network Open

arch-xc7

f4pga/f4pga-arch-defs#546 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Drop tinyfpga-b2 support Open

arch-ice40

f4pga/f4pga-arch-defs#552 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
dram test doesn't work in sim Open

f4pga/f4pga-arch-defs#558 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Rely on external package management as much as possible Open

type-build

f4pga/f4pga-arch-defs#559 · 7 comments · 2 reactions · 0 assignees · Indexed Sep 15, 2026
Improve CI Open

f4pga/f4pga-arch-defs#568 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Rename `library` to `common/verilog` Open

f4pga/f4pga-arch-defs#571 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add SymbiYosys support for equivalence testing Open

f4pga/f4pga-arch-defs#572 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Improve xc7 fasm2verilog output Open

arch-xc7 enhancement good first issue help wanted

f4pga/f4pga-arch-defs#578 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Consider adding a pre-yosys Verilator lint check Open

enhancement help wanted lang-makefile lang-verilog type-build type-infra type-sim

f4pga/f4pga-arch-defs#590 · 1 comment · 2 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Add features to enable replacing handwritten XML with generated from `.sim.v` files Open

f4pga/f4pga-arch-defs#595 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Solve issues to have working tests Open

arch-* lang-verilog lang-xml type-sim type-utils type-vpr

f4pga/f4pga-arch-defs#599 · 24 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Rename distributed ram (DRAM) to LUT ram Open

arch-xc7

f4pga/f4pga-arch-defs#616 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
More than 2 RAM32X1Ds can be packed in a slice Open

arch-xc7

f4pga/f4pga-arch-defs#618 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Documentation implies multiple LUT modes, but there is only one. Open

arch-xc7

f4pga/f4pga-arch-defs#619 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Why is there a bram_l and bram_r which are identical? Open

arch-xc7 cleanup

f4pga/f4pga-arch-defs#621 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Write documentation about why the stub is needed to create dual port 128 LUT RAM Open

arch-xc7

f4pga/f4pga-arch-defs#622 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add schema checks to make sure all block have metadata Open

arch-* help wanted lang-xml type-vpr

f4pga/f4pga-arch-defs#623 · 12 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add format_cmake target to auto-format CMakefile.txt files? Open

f4pga/f4pga-arch-defs#625 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Clean up the top level directory Open

f4pga/f4pga-arch-defs#626 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Add v2x for Figure 46 - Multiclock Dual Port RAM Open

arch-* lang-verilog

f4pga/f4pga-arch-defs#629 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Add test for Figure 43 - Mixed sequential/combinational single port ram Open

arch-* lang-verilog

f4pga/f4pga-arch-defs#630 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Add test for Figure 44 - Sequential single port ram Open

arch-* lang-verilog

f4pga/f4pga-arch-defs#631 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: Add test for Figure 45 - Sequential single port ram with a combinational input Open

arch-* lang-verilog

f4pga/f4pga-arch-defs#632 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
v2x: simple_pll test needs a pb_type Open

f4pga/f4pga-arch-defs#633 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

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