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f4pga

6 indexed repositories · View on GitHub

prjxray
Documenting the Xilinx 7-series bit-stream format.

Python · 914 stars
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Jupyter Notebook · 314 stars
ideas
Random ideas and interesting ideas for things we hope to eventually do.

86 stars
prjuray
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

SystemVerilog · 84 stars
f4pga-website

SCSS · 3 stars
actions
GitHub Actions to be reused in CI workflows

Python · 2 stars

Open All

512 open issues indexed

Vendor Tools IO placement error Open

f4pga/f4pga-arch-defs#1429 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Primitives for the post-layout simulations Open

f4pga/f4pga-arch-defs#1436 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add license automated check in Travis Open

f4pga/f4pga-arch-defs#1438 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
QuickLogic: incomplete generated sdf files Open

f4pga/f4pga-arch-defs#1441 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
OpenTitan support Open

f4pga/f4pga-arch-defs#1442 · 15 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Install at custom location Open

f4pga/f4pga-arch-defs#1443 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Announce master build failures on the IRC channel Open

type-infra

f4pga/f4pga-arch-defs#1451 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Issue in the top_bit.v with respect to ASSP port map Open

f4pga/f4pga-arch-defs#1454 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Issue in the top_bit.v, driving a output ASSP port Open

f4pga/f4pga-arch-defs#1455 · 3 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Issue in the top_bit.v with respect to RAMFIFO port maps Open

f4pga/f4pga-arch-defs#1458 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Issue in the top_bit.v with respect to Multiplier port mapping Open

f4pga/f4pga-arch-defs#1459 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
"OpenTitan RTL synthesis with Yosys" in hardenedlinux Open

f4pga/f4pga-arch-defs#1465 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Quicklogic: make target related to analysis is failing Open

f4pga/f4pga-arch-defs#1467 · 6 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Create a parser for the UCF file format Open

project-verilog-to-routing type-coding

f4pga/ideas#1 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Quicklogic: ram testcase failure Open

f4pga/f4pga-arch-defs#1472 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Solve the problem of automatic IDELAYCTRL placement Open

f4pga/f4pga-arch-defs#1481 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Create a parser for the XDC file format Open

project-verilog-to-routing type-coding

f4pga/ideas#2 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Quicklogic: Router run time very high Open

f4pga/f4pga-arch-defs#1486 · 8 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Rewrite the `.echo` file output from vpr to be auto-generated. Open

project-verilog-to-routing type-coding

f4pga/ideas#3 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
VPR route designs through unknown GTP PIPs Open

f4pga/f4pga-arch-defs#1489 · 6 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Rewrite the xml parser in vpr to be based on DTD and auto generated. Open

project-verilog-to-routing type-coding

f4pga/ideas#4 · 7 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Missing IOB timings in xc7 Open

f4pga/f4pga-arch-defs#1503 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add support EDIF to Verilog to Routing Open

project-verilog-to-routing type-coding

f4pga/ideas#5 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Problematic OBUFT routing in Vivado Open

f4pga/f4pga-arch-defs#1514 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add support for reading EDIF to Yosys Open

project-yosys type-coding

f4pga/ideas#6 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Lots of new lines in the log output makes it hard to read. Open

f4pga/f4pga-arch-defs#1516 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Unknown HCLK_R bits Open

f4pga/f4pga-arch-defs#1529 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 15, 2026
consolidate to using a single json module in python code Open

parts-tools

f4pga/prjxray#763 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch : Quicklogic : Failed to find matching architecture model for 'mux4x0' Open

f4pga/f4pga-arch-defs#1537 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add tool for merging SDF files Open

f4pga/prjxray#776 · 4 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Branch : Quicklogic : Failed to find matching architecture model for 'logic_cell_macro' Open

f4pga/f4pga-arch-defs#1543 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Terminate the looping fuzzers when TODO list stops changing Open

f4pga/prjxray#777 · 11 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Branch: Quicklogic: current techmap does not handle FIFO_DIR routed to non-constant Open

f4pga/f4pga-arch-defs#1544 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Make docs build not recreate links every time something is changed, only when a specific file was changed Open

enhancement parts-docs

f4pga/prjxray#781 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch Quicklogic : The latest global clock support has issues Open

f4pga/f4pga-arch-defs#1553 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Cross link how to use base address and word offset Open

parts-docs

f4pga/prjxray#803 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Branch Quicklogic : The no of PB-5XGMUX available shows only 1. Open

f4pga/f4pga-arch-defs#1554 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Branch Quicklogic: No routing path for connection to sink_rr 14092 Open

f4pga/f4pga-arch-defs#1556 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add the tile wire, pip, site pin diagram Open

parts-docs

f4pga/prjxray#804 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Branch Quicklogic : Target <design>_chandalar_bit_v does not build Open

f4pga/f4pga-arch-defs#1557 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Check if PIPs outside of the INT switch box has regular bit pattern Open

parts-docs

f4pga/prjxray#805 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
xc/xc7/fasm2bels/make_routes.py should be rewritten to not be recursive Open

f4pga/f4pga-arch-defs#1559 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Check info about fake pips in INT switch box? Open

parts-docs

f4pga/prjxray#806 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Remove `test` from full-devices that are packed in the install tarball Open

f4pga/f4pga-arch-defs#1578 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Add reference tileconn as documentation Open

parts-docs

f4pga/prjxray#807 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Expand segment bit positions section Open

parts-docs

f4pga/prjxray#808 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Fix out of date .bits example Open

parts-docs

f4pga/prjxray#812 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 15, 2026
Fix the bullet points in .bits example Open

parts-docs

f4pga/prjxray#813 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Document bits for HCLK_[LR]_BOT_UTURN tiles Open

f4pga/prjxray#894 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026
Fuzzers vulnerable to incorrect locale settings. Open

f4pga/prjxray#910 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 15, 2026

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