f4pga / f4pga/f4pga-arch-defs

[xc7] Packer inter cluster delay should be seeded from routing data

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Description

The VPR inter cluster delay (https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/065a62fc9b7e295873e90158295f207754b72025/vpr/src/base/vpr_api.cpp#L512) is computed using switches determined from ``get_intercluster_switch_fanin_estimates``. This implies means that the switch definition used in the architecture is used, rather than the one from the rrgraph. This switch should have a realistic ``Tdel`` to ensure that the inter cluster delay is approximately correctly.

An alternative approach might be to specific the inter-cluster delay directly, which is not currentlty supported by VPR.

Currently the xc7 delay value is statically set in prjxray_arch_import.py (https://github.com/SymbiFlow/symbiflow-arch-defs/pull/760/files#diff-5b49c38923968b342d6c9cad00f75a0aL560), but this should eventually be sourced from the timing data in the database.

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