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SpinalHDL

5 indexed repositories · View on GitHub

VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation

Assembly · 3265 stars
SpinalHDL
Scala based HDL

Scala · 2040 stars
VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger

Scala · 253 stars
SpinalDoc-RTD
The sources of the online SpinalHDL doc

Python · 32 stars
NaxSoftware

C · 13 stars

Beginner friendly Everything

Open All

sstatus exposes mstatus.MPRV at bit 17 and lets S-mode write it Open

Difficulty 2/5 1-3 hours Newbie friendliness 84/100

SpinalHDL/VexRiscv#484 · Opened Sep 12, 2026
[Feature Request] Add `toInt` and `toBigInt` helper methods to `SpinalEnumElement` Open

Difficulty 2/5 1-3 hours Newbie friendliness 76/100

SpinalHDL/SpinalHDL#1960 · Opened Sep 8, 2026
In ClockDomain.internal: Clock enable signal name derived from resetActiveLevel instead of clockEnableActiveLevel Open

Difficulty 1/5 Under an hour Newbie friendliness 85/100

SpinalHDL/SpinalHDL#1952 · Opened Aug 24, 2026
MSYS2 Verilator URL 404 Open

Difficulty 2/5 1-3 hours Newbie friendliness 68/100

SpinalHDL/SpinalDoc-RTD#311 · 4 comments · Opened Jul 10, 2026
Axi4Stream user signal width should not be multiplied by data width Open

Difficulty 2/5 1-3 hours Newbie friendliness 78/100

SpinalHDL/SpinalHDL#1294 · 2 comments · Opened Jan 23, 2024

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