SpinalHDL/VexRiscv

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A FPGA friendly 32 bit RISC-V CPU implementation

Stars: 3.3k
Forks: 517
Open beginner issues: 0
Indexed issues: 138
Avg merge: 4d 7h
Merged PRs (30d): 3

Dominant language: Assembly
License: MIT
Last GitHub push: Aug 31, 2026
Latest indexed: Sep 19, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
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138 open issues indexed

[Formal finding VEX-RTL-019] medelegh is not implemented on an XLEN=32 hart with S-mode, so the upper half of the 64-bit medeleg is unreachable and a read traps Open

Difficulty 4/5 3-5 days Newbie friendliness 45/100

SpinalHDL/VexRiscv#498 · Opened Sep 18, 2026
[Formal finding VEX-RTL-016] scause implements only 4 bits of Exception Code, but the architecture requires bits 4-0 so the register can hold 0-31 Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

SpinalHDL/VexRiscv#497 · Opened Sep 18, 2026
[Formal finding VEX-RTL-015] menvcfg and menvcfgh are not implemented on a hart with U-mode and S-mode, so reads of them raise illegal-instruction exceptions Open

Difficulty 4/5 3-5 days Newbie friendliness 52/100

SpinalHDL/VexRiscv#496 · Opened Sep 18, 2026
[Formal finding VEX-RTL-014] sepc has no low-bit masking: sepc[0] is writable and reads back as one Open

Difficulty 3/5 1-2 days Newbie friendliness 55/100

SpinalHDL/VexRiscv#495 · Opened Sep 18, 2026
[Formal finding VEX-RTL-011] mstatus.MPRV is not writable on a hart that implements U-mode Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

SpinalHDL/VexRiscv#494 · Opened Sep 18, 2026
[Formal finding VEX-RTL-010] misa.Extensions reports B and G and omits I on a core that implements RV32I, and the E bit is not the complement of I Open

Difficulty 4/5 3-5 days Newbie friendliness 45/100

SpinalHDL/VexRiscv#493 · Opened Sep 18, 2026
[Formal finding VEX-RTL-007] mtval is not written on an interrupt trap, so it retains the faulting address left by the previous exception instead of being set to zero Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

SpinalHDL/VexRiscv#492 · Opened Sep 18, 2026
[Formal finding VEX-RTL-006] mcause has no reset value, so after reset it reads an undefined value instead of one indicating the cause of the reset Open

Difficulty 3/5 1-2 days Newbie friendliness 52/100

SpinalHDL/VexRiscv#491 · Opened Sep 18, 2026
[Formal finding VEX-RTL-004] On an environment-call exception mtval is written with the ECALL instruction encoding instead of zero Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

SpinalHDL/VexRiscv#490 · Opened Sep 18, 2026
[Formal finding VEX-RTL-003] mepc has no low-bit masking: mepc[0] is writable and reads back as one, and MRET then redirects the fetch to an unaligned address Open

Difficulty 4/5 3-5 days Newbie friendliness 45/100

SpinalHDL/VexRiscv#489 · Opened Sep 18, 2026
[Formal finding VEX-RTL-002] MRET sets mstatus.MPP to 00 (U-mode) on a hart that implements only M-mode, leaving an unsupported privilege encoding architecturally readable Open

Difficulty 4/5 3-5 days Newbie friendliness 38/100

SpinalHDL/VexRiscv#488 · Opened Sep 18, 2026
MMU plugin allows supervisor execution of code in user pages when status.SUM is 1 Open

Difficulty 3/5 1-2 days Newbie friendliness 68/100

SpinalHDL/VexRiscv#487 · 1 comment · Opened Sep 17, 2026
mcounteren (0x306) and scounteren (0x106) are not implemented on harts with U-mode / S-mode Open

Difficulty 3/5 1-2 days Newbie friendliness 72/100

SpinalHDL/VexRiscv#486 · Opened Sep 12, 2026
mstatus.TVM / TW / TSR are hardwired to zero on configurations with S-mode and U-mode Open

Difficulty 4/5 3-5 days Newbie friendliness 55/100

SpinalHDL/VexRiscv#485 · Opened Sep 12, 2026
sstatus exposes mstatus.MPRV at bit 17 and lets S-mode write it Open

Difficulty 2/5 1-3 hours Newbie friendliness 84/100

SpinalHDL/VexRiscv#484 · Opened Sep 12, 2026
Critical Failure on Anlogic TD based FPGA with Murax Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexRiscv#482 · Opened Aug 28, 2026
Question about EmbeddedRiscvJtag, DebugPlugin, and OpenOCD debugging via Xilinx BSCANE2 Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexRiscv#479 · Opened Aug 5, 2026
Questions: APB3 ArrayBuffer via Apb3Decoder & CPU M plugin Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexRiscv#477 · Opened Jun 1, 2026
Question and puzzling about prebuilt Hex under resource folder for Murax demo Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexRiscv#476 · 2 comments · Opened May 23, 2026
share Risc-V knowledge for Future Digital Civilization Technology Open

Difficulty 5/5 Over a week Newbie friendliness 15/100

SpinalHDL/VexRiscv#474 · Opened May 3, 2026
Assertion with configuration Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexRiscv#473 · 1 comment · Opened Mar 8, 2026
How do I add VexRiscv as a dependency in a mill project Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#472 · 3 comments · Opened Mar 1, 2026
What is the cycle latency of VexRiscv FPU double‑precision add (FADD.D), and how can I derive it from the RTL/config? Open

Difficulty 4/5 3-5 days Newbie friendliness 30/100

SpinalHDL/VexRiscv#469 · 1 comment · Opened Jan 22, 2026
[Bug] CSR writes to cycle/instret do not raise illegal-instruction Open

Difficulty 4/5 3-5 days Newbie friendliness 42/100

SpinalHDL/VexRiscv#465 · 1 comment · Opened Nov 24, 2025
[Bug] VexRiscv FSGNJX.D Sign Bit Wrong Open

Difficulty 3/5 1-2 days Newbie friendliness 45/100

SpinalHDL/VexRiscv#464 · 1 comment · Opened Nov 24, 2025
How to add RV32IMAF instructions to a modified Murax SoC? Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexRiscv#461 · 3 comments · Opened Nov 13, 2025
Briey Soc + HDMI +SD_card Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexRiscv#460 · 1 comment · Opened Nov 13, 2025
Question about VexRiscv Debug Interface and onChipRam Behavior in Murax on Arty-A7 Open

Difficulty 4/5 3-5 days Newbie friendliness 15/100

SpinalHDL/VexRiscv#459 · 2 comments · Opened Nov 5, 2025
Seeking Advice on Murax SoC RAM Access and Floating-Point Support Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexRiscv#458 · 1 comment · Opened Oct 22, 2025
Fails with `scala.NotImplementedError: an implementation is missing` Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#456 · 1 comment · Opened Oct 19, 2025
How to configure the on-chip RAM size Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#452 · 4 comments · Opened Jun 8, 2025
Integrating vhdl using Blackbox Open

Difficulty 4/5 3-5 days Newbie friendliness 30/100

SpinalHDL/VexRiscv#451 · 5 comments · Opened Jun 4, 2025
Porting FREERTOS to VexRiscv Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexRiscv#448 · 5 comments · Opened Apr 21, 2025
Vexriscv dual-core smp architecture has a problem when debugging Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#446 · 8 comments · Opened Mar 11, 2025
Partitioning On-Chip RAM in Murax SoC and Mapping IP Access Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#443 · 3 comments · Opened Feb 12, 2025
Any way to replace 'Area' with 'Component' in plugin's implementation? Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#441 · 5 comments · Opened Jan 21, 2025
How to add extra memory to proessor Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#439 · 5 comments · Opened Jan 14, 2025
custom FPU Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#438 · 1 comment · Opened Jan 14, 2025
Do you have plan to add FPU area timing option for vexriscv like vexii? Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#436 · 2 comments · Opened Dec 25, 2024
VexRiscv for custom processing in memory instructions Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#420 · 2 comments · Opened Aug 7, 2024
AxiCrossBar with Standard Axi4 Interface in Briey Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#406 · 15 comments · Opened May 6, 2024
How to only modify certain one reset kind of specific Reg in vex core. Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#404 · 1 comment · Opened Apr 22, 2024
Compile C code and run bare metal cycle accurate simulation Open

Difficulty 4/5 3-5 days Newbie friendliness 30/100

SpinalHDL/VexRiscv#395 · 3 comments · Opened Mar 6, 2024
EU Funding Open

Difficulty 5/5 Over a week Newbie friendliness 15/100

SpinalHDL/VexRiscv#393 · 3 comments · Opened Mar 1, 2024
Data Stream in/out SoC <-> FPGA Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexRiscv#391 · 6 comments · Opened Feb 6, 2024
DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#389 · 3 comments · Opened Feb 4, 2024
Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.) Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#385 · 1 comment · Opened Dec 15, 2023
debug Open

Difficulty 5/5 Over a week Newbie friendliness 10/100

SpinalHDL/VexRiscv#384 · 1 comment · Opened Dec 12, 2023
Murax XIP compile issue Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexRiscv#380 · 11 comments · Opened Nov 24, 2023
compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216 Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexRiscv#362 · 1 comment · Opened Sep 5, 2023

SpinalHDL/VexRiscv

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