SpinalHDL/VexiiRiscv

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Like VexRiscv, but, Harder, Better, Faster, Stronger

Stars: 253
Forks: 67
Open beginner issues: 0
Indexed issues: 26
Avg merge: 8d 12h
Merged PRs (30d): 6

Dominant language: Scala
License: MIT
Last GitHub push: Sep 18, 2026
Latest indexed: Sep 19, 2026
Contributing guide: No contributing guide
Code of conduct: No code of conduct
Beginner labels: No beginner labels indexed

Beginner friendly Everything

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26 open issues indexed

About CFU Request/Reorder Open

Difficulty 5/5 Over a week Newbie friendliness 30/100

SpinalHDL/VexiiRiscv#155 · 15 comments · Opened Aug 1, 2026
[DISCUSSION] Unified configuartion database for VexiiRiscv Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#152 · 1 reaction · Opened Jul 21, 2026
MMU memory access in cacheless LSU is bypassed without PMP check. Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

SpinalHDL/VexiiRiscv#145 · 2 comments · Opened Jul 9, 2026
Are bitmanip extensions (Zba, Zbb, Zbc, Zbs) still experimental, can we add them to the README and the RTD ? Open

Difficulty 3/5 1-2 days Newbie friendliness 48/100

SpinalHDL/VexiiRiscv#140 · 2 comments · Opened Jun 7, 2026
Is software prefetch (Zicbop from CMO) fully or partially implemented ? Open

Difficulty 4/5 3-5 days Newbie friendliness 48/100

SpinalHDL/VexiiRiscv#139 · Opened Jun 7, 2026
Issue with embedding VexiiRiscv into larger design Open

Difficulty 4/5 3-5 days Newbie friendliness 38/100

SpinalHDL/VexiiRiscv#134 · 1 comment · Opened May 28, 2026
Request for Zacas extension support Open

Difficulty 5/5 Over a week Newbie friendliness 30/100

SpinalHDL/VexiiRiscv#125 · 5 comments · Opened Apr 14, 2026
Separate instruction and data memories Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#124 · 3 comments · Opened Apr 2, 2026
Adding SDRAM to MicroSoC Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#122 · 3 comments · Opened Mar 15, 2026
MRET causes illegal instruction trap after ECALL in/from M-Mode Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#117 · 3 comments · Opened Feb 12, 2026
Strange CPU Behavior attempting to port from VexRiscv to VexiiRiscv Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#114 · 7 comments · Opened Feb 6, 2026
Redundant tracer initialization for harts Open

Difficulty 2/5 1-3 hours Newbie friendliness 45/100

SpinalHDL/VexiiRiscv#111 · 1 comment · Opened Jan 30, 2026
How to use external JTAG (CMSIS-DAP) with Vexii MicroSoc? (Beginner) Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#105 · 3 comments · Opened Jan 9, 2026
Examples for simulate SoC with spi flash? Open

Difficulty 4/5 3-5 days Newbie friendliness 42/100

SpinalHDL/VexiiRiscv#102 · 6 comments · Opened Dec 22, 2025
There is an inconsistency in mie.LCOFIE Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#96 · 2 comments · Opened Nov 16, 2025
Trying to connect a LsuL1Cmd port from external units (like CFU) to CPU Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#80 · 6 comments · Opened Sep 3, 2025
[Feature request] Zmmul extension, no division Open

Difficulty 4/5 3-5 days Newbie friendliness 45/100

SpinalHDL/VexiiRiscv#73 · 3 comments · Opened Aug 22, 2025
Disable LSU Cache on LiteX SoC Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#68 · 1 comment · Opened Aug 1, 2025
How to tunnel VexiiRiscv Debug port using BSCANE2? Open

Difficulty 4/5 3-5 days Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#58 · 7 comments · Opened May 27, 2025
[Feature Request] Vector extensions Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#57 · 5 comments · 1 reaction · Opened May 24, 2025
"Hello world" tutorial fails to compile Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#56 · Opened May 23, 2025
Support for vectored interrupt mode? Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#53 · 3 comments · Opened Apr 20, 2025
How to extract RS1/RS2 value for debugging? Open

Difficulty 4/5 3-5 days Newbie friendliness 35/100

SpinalHDL/VexiiRiscv#46 · Opened Mar 19, 2025
Is there anyway to generate with ICache and a extra cacheless I-channel？ Open

Difficulty 5/5 Over a week Newbie friendliness 25/100

SpinalHDL/VexiiRiscv#39 · 1 comment · Opened Jan 13, 2025
ti375 devkit litex debian demo Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexiiRiscv#24 · 28 comments · 3 reactions · Opened Sep 4, 2024
Roadmap / Contributing Open

Difficulty 5/5 Over a week Newbie friendliness 20/100

SpinalHDL/VexiiRiscv#1 · 18 comments · 15 reactions · Opened Nov 14, 2023

SpinalHDL/VexiiRiscv

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